Split embedded DRAM processor

• US 6,760,833 B1
• Filed: 08/31/2000
• Issued: 07/06/2004
• Est. Priority Date: 08/01/1997
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Dowling, Eric M.
• Primary Examiner(s): TREAT, WILLIAM M
• Application Number:
  US09/652,638
• Time in Patent Office: 1,405 Days
• Field of Search: 712/34, 711/105
• US Class Current: 712/34
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor.

Claims

1. An embedded dynamic random access memory (DRAM) coprocessor system implemented as a plurality of individual bit slice units having single in-line memory module (SIMM) interface connectors adapted for interchange with standard DRAM SIMMs disposed on electronic component boards.

2. The embedded DRAM coprocessor system of claim 1, further comprising an additional interface connector which connects at least two of the embedded DRAM bit slice units together via a separate bus not found on the computer board into which the bit slice units are plugged.

3. The embedded DRAM coprocessor system of claim 1, wherein the bit slice width of the each SIMM multiplied by the number of SIMMs in the system is equal to the bus word width of the processor with which the memory modules are in data communication.

4. The embedded DRAM coprocessor system of claim 2, further comprising a communications interface adapted for data communication between respective ones of said individual bit slice units via said bus.

5. An embedded dynamic random access memory (DRAM) coprocessor comprising individual means for bit slicing, said means for bit slicing having in-line memory module (SIMM) interface means for interfacing with respective in-lime memory module slots disposed on an electronic component board.

6. The embedded DRAM coprocessor of claim 5, further comprising:

interface connector means for connecting at least two of the means for bit slicing together via a separate bus means not found on the computer board into which the individual means for bit slicing are plugged; and

communications interface means for communicating data between said at least two means for bit slicing via said bus means.

7. A method of communicating data between an embedded DRAM processor and a host computing system having an electronics board with a plurality of SIMM interfaces, comprising:

providing a plurality of embedded DRAMs in the form of bit slice units;

connecting each of said plurality of bit slice units to said electronics board via respective ones of said SIMM interfaces;

connecting at least two of said plurality of bit slice units together using at least one bus;

transferring data between at least one of said bit slice units and said host system; and

transferring data between said at least two bit slice units.

8. The method of claim 7, further comprising configuring said at least two bit slice units to communicate data with each other.

9. A method of accelerating the processing of data on a host computing system having an electronics board with a plurality of SIMM interfaces, and a host processor in data conmmunication with said electronics board, comprising:

providing a plurality of embedded DRAMs coprocessors in the form of bit slice units, said bit slice units being adapted for processing data in cooperation with said host processor;

connecting each of said plurality of bit slice units to said electronics board via respective ones of said SIMM interfaces;

connecting at least two of said plurality of bit slice units together using at least one bus; and

executing a computer program on at least said host processor, said act of executing initiating the acts of;

transferring data between at least one of said bit slice units and said host system;

transferring data between said at least two bit slice units; and

processing at least a portion of said data transferred between said at least one bit slice unit and said host system using at least one of said bit slice units;

wherein the acts of transferring and processing accelerate the processing of data within said host system.

10. The method of claim 9, further comprising configuring said at least two bit slice units to communicate data with each other.

11. An embedded dynamic random access memory (DRAM) coprocessor system comprising:

a plurality of individual bit slice units, each bit slice unit comprising;

a plurality of DRAM cells;

a processing unit; and

a communications interface adapted for data communication with at least one other bit slice unit.

12. The embedded DRAM coprocessor system of claim 11, whereby each bit slice unit is implemented on a separate die.

13. The embedded DRAM coprocessor system of claim 11, whereby each bit slice unit is implemented on a separate memory module circuit board.

14. The embedded DRAM coprocessor system of claim 13, whereby each memory module circuit board is a single in-line memory module (SIMM) adapted for interchange with standard DRAM SIMMs disposed on electronic component boards.

15. The embedded DRAM coprocessor system of claim 13, wherein at least two memory module circuit board further comprise:

a SIMM connector interface adapted for interchange with standard DRAM SIMMs disposed on electronic component boards and for communication with a host processor; and

at least one bus connector interface adapted for interconnection with at least one other memory module circuit board containing one of said bit slice units.

16. The embedded DRAM coprocessor system of claim 11, further comprising:

one or more module circuit boards adapted for interchange with standard DRAM SIMMs disposed on electronic component boards;

whereby onto each of said memory module circuit boards is mounted a single bit slice unit.

17. The embedded DRAM coprocessor system of claim 11, whereby a host computer sends at least one instruction to at least one of said bit slice units to cause at least two of said bit slice units to process data stored within in their respective DRAM cells, and said bit slice units pass data therebetween using said communication interface.

18. In a processing system comprising a host processor coupled to an embedded DRAM coprocessor subsystem, whereby said embedded DRAM coprocessor comprises a plurality of individual bit slice units, each bit slice unit comprising an array of DRAM cells, a processing unit, and a communications interface adapted for data communication with at least one other bit slice unit, a method comprising:

storing a data structure as a distributed object having components in at least two of said arrays of DRAM cells;

sending a command from said processor to at least one of said bit slice units over a first data bus adapted to support communication between said processor and said embedded DRAM coprocessor subsystem;

executing in at least two of said bit slice units at least one program to process portions of said distributed data object stored in respective arrays of DRAM cells using the respective processing unit; and

passing at least one bit of information between said at least two bit slice units using said communications interface in support of the act of executing.

19. The method of claim 18, whereby the act of sending further involves passing said at least one instruction to said at least one bit slice unit via a single in-line memory module (SIMM) interface connector adapted for interchange with standard DRAM SIMMs disposed on electronic component boards.

20. The method of claim 19, whereby said host processor is mounted on a mother board, at least one bit slice unit is mounted on sub-circuit board comprising said single in-line memory module (SIMM) interface connector, said single in-line memory module (SIMM) interface connector is connected to said mother board, and the act of passing involves sending said at least one bit of information is across an inter-SIMM interface connector involving a data path that is not a part of the motherboard.