Method and mechanism for performing improved timing analysis on virtual component blocks

• US 6,760,894 B1
• Filed: 06/14/2002
• Issued: 07/06/2004
• Est. Priority Date: 12/28/1999
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Yalcin, Hakan, Palermo, Robert J., Mortazavi, Mohammad S., Bamji, Cyrus S.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Dinh, Paul
• Application Number:
  US10/173,202
• Time in Patent Office: 753 Days
• Field of Search: 716/1, 716/4-6, 716/18, 716/7, 716/10, 703/19
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method and mechanism for performing a timing analysis on virtual component blocks, which is an abstraction of a circuit block is provided. A set of modes for a circuit block are identified, where a mode is a set of meaningful control input values. Each functionally meaningful or useful control input combination is applied to the circuit block. For each control input combination applied, a delay for each data input/output path and each control input/output path not passing through a blocked circuit node for the applied combination of control inputs is calculated. The delay information for the data paths and control paths is stored within a timing model. The delay information may include a maximum or minimum delay for the circuit block. The timing of sequential circuit blocks may also characterized using the methods and mechanisms herein.

Claims

1. A method of analyzing timing in a circuit block, said circuit block including a plurality of inputs and a plurality of outputs, said plurality of inputs divided into a set of one or more data inputs and a set of one or more control inputs, said method comprising:

(a) identifying a set of modes, each of said modes corresponding to a unique combination of control input values for the circuit block;

(b) applying the combination of control input values for one of said modes to the circuit block;

(c) for each data input, calculating a first delay for each data input/output path not passing through a blocked circuit node for the applied-combination of control input values using a first propagation condition;

(d) for each control input, calculating a second delay for each control input/output path not passing through a blocked circuit node for the applied combination of control input values using a second propagation condition; and

(e) repeating steps (b) through (d) for each of the remaining modes within the set of modes.

2. The method of claim 1, wherein the second propagation condition is one member selected from the group consisting of viability, safe static, static co-sensitization, and the Brand-Iyengar condition.

3. The method of claim 1, further comprising:

(f) storing a timing model, wherein the timing model comprises information about, for each mode, the first delay and the second delay.

4. The method of claim 3, wherein the timing model comprises information about the maximum delay of the first delay, the maximum delay of the second delay, the minimum delay of the first delay, and the minimum delay of the second delay.

5. The method of claim 3, further comprising analyzing the timing of a virtual component block using the timing model.

6. The method of claim 1, wherein step (b) comprises propagating a constant for each control input value.

7. The method of claim 1, wherein the first propagation condition is static sensitization.

8. The method of claim 1, wherein one or more false paths are excluded from the calculation of the first delay or the calculation of the second delay.

9. The method of claim 1, further comprising:

(f) verifying the timing of the circuit block using the set of first delays and the set of second delays calculated in step (c) and step (d).

10. The method of claim 9, wherein the second delay is less pessimistic than topological delay.

11. The method of claim 1, wherein the first delay and the second delay are m*n matrices of a scalar quantity.

12. The method of claim 1, wherein the first delay is a maximum delay for each data input/output path and the second delay is a maximum delay for each control input/output path.

13. The method of claim 1, wherein the first delay is a minimum delay for each data input/output path and the second delay is a minimum delay for each control input/output path.

14. The method of claim 1, wherein the circuit block is a sequential circuit block, further comprising:

(f) calculating a clock model using the set of first delays and the set of second delays calculated in step (c) and step (d).

15. The method of claim 14, further comprising:

(g) storing the clock model.

47. The method of claim 1, wherein the circuit block is sequential, the method further comprising:

generating a mode-dependent clock model of the sequential circuit.

48. The method of claim 47, wherein generating the mode-dependent clock model further comprises:

generating, for each mode i, a clock model CM_i that ignores the control input signals;

generating a clock model CM_c that ignores the data input signals; and

determining a mathematical union of the clock models CM_i and CM_c for each mode i.

16. A computer-readable medium carrying one or more sequences of instructions for analyzing timing in a circuit block, said circuit block including a plurality of inputs and a plurality of outputs, said plurality of inputs divided into a set of one or more data inputs and a set of one or more control inputs, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform a method comprising:

(a) identify a set of modes, each of said modes corresponding to a unique combination of control input values for the circuit block;

(b) apply the combination of control input values for one of said modes to the circuit block;

(c) for each data input, calculate a first delay for each data input/output path not passing through a blocked circuit node for the applied combination of control input values using a first propagation condition;

(d) for each control input, calculate a second delay for each control input/output path not passing through a blocked circuit node for the applied combination of control input values using a second propagation condition; and

(e) repeat steps (b) through (d) for each of the remaining modes within the set of modes.

17. The computer-readable medium of claim 16, wherein the second propagation condition is one member selected from the group consisting of viability, safe static, static co-sensitization, and the Brand-Iyengar condition.

18. The computer-readable medium of claim 16, wherein execution of the one or more sequences of instructions by one or more processors further causes the one or more processors to:

(f) store a timing model, wherein the timing model comprises information about, for each mode, the first delay and the second delay.

19. The computer-readable medium of claim 18, wherein the timing model comprises information about the maximum delay of the first delay, the maximum delay of the second delay, the minimum delay of the first delay, and the minimum delay of the second delay.

20. The computer-readable medium of claim 18, wherein execution of the one or more sequences of instructions by one or more processors further causes the one or more processors to analyze the timing of a virtual component block using the timing model.

21. The computer-readable medium of claim 16, wherein step (b) comprises propagating a constant for each control input value.

22. The computer-readable medium of claim 16, wherein the first propagation condition is static sensitization.

23. The computer-readable medium of claim 16, wherein one or more false paths are excluded from the calculation of the first delay or the calculation of the second delay.

24. The computer-readable medium of claim 16, wherein execution of the one or more sequences of instructions by one or more processors further causes the one or more processors to:

(f) verify the timing of the circuit block using the set of first delays and the set of second delays calculated in step (c) and step (d).

25. The computer-readable medium of claim 24, wherein the second delay is less pessimistic than topological delay.

26. The computer-readable medium of claim 16, wherein the first delay and the second delay are m*n matrices of a scalar quantity.

27. The computer-readable medium of claim 16, wherein the first delay is a maximum delay for each data input/output path and the second delay is a maximum delay for each control input/output path.

28. The computer-readable medium of claim 16, wherein the first delay is a minimum delay for each data input/output path and the second delay is a minimum delay for each control input/output path.

29. The computer-readable medium of claim 16, wherein the circuit block is a sequential circuit block, and wherein execution of the one or more sequences of instructions by one or more processors further causes the one or more processors to:

(f) calculate a clock model using the set of first delays and the set of second delays calculated in step (c) and step (d).

30. The computer-readable medium of claim 29, wherein execution of the one or more sequences of instructions by one or more processors further causes the one or more processors to:

(g) store the clock model.

31. An apparatus for analyzing timing in a circuit block, said circuit block including a plurality of inputs and a plurality of outputs, said plurality of inputs divided into a set of one or more data inputs and a set of one or more control outputs, said apparatus comprising:

means for identifying a set of modes, each of said modes corresponding to a unique combination of control input values for the circuit block;

means for applying the combination of control input values for one of said modes to the circuit block;

means for calculating, for each data input, a first delay for each data input/output path not passing through a blocked circuit node for the applied combination of control input values using a first propagation condition; and

means for calculating, for each control input, a second delay for each control input/output path not passing through a blocked circuit node for the applied combination of control input values using a second propagation condition.

32. The apparatus of claim 31, wherein the second propagation condition is one member selected from the group consisting of:

viability, safe static, static co-sensitization, and the Brand-Inyengar condition.

33. The apparatus of claim 31, further comprising:

means for storing a timing model, wherein the timing model comprises information about, for each mode, the first delay and the second delay.

34. The apparatus of claim 33, wherein the timing model comprises information about the maximum delay of the first delay, the maximum delay of the second delay, the minimum delay of the first delay, and the minimum delay of the second delay.

35. The apparatus of claim 31, wherein said means for applying the combination of control input values for one of said modes to the circuit block comprises means for propagating a constant for each control input value.

36. The apparatus of claim 31, wherein the first propagation condition is static sensitization.

37. The apparatus of claim 31, wherein one or more false paths are excluded from the calculations of the first delay or the claculation of the second delay.

38. The apparatus of claim 31, further comprising:

means for verifying the timing of the circuit block using the set of first delays and the set of second delays.

39. The apparatus of claim 38, wherein the second delay is less pessimistic than topological delay.

40. The apparatus of claim 31, wherein the first delay and the second delay are m*n matrices of a scalar quantity.

41. The apparatus of claim 31, wherein the first delay is a maximum delay for each data input/output path and the second delay is a maximum delay for each control input/output path.

42. The apparatus of claim 31, wherein the first delay is a minimum delay for each data input/output path and the second delay is a minimum delay for each control input/output path.

43. The apparatus of claim 31, wherein the circuit block is a sequential circuit block, further comprising:

means for calculating a clock model using the set of first delays and the set of second delays.

44. The apparatus of claim 43, further comprising:

means for storing the clock model.

45. The apparatus of claim 31, wherein the circuit block is sequential, the apparatus further comprising:

means for generating a mode-dependent clock model of the sequential circuit.

46. The apparatus of claim 45, wherein said means for generating the mode-dependent clock model further comprises:

means for generating, for each mode i, a clock model CM_i that ignores the control input signals;

means for generating a clock model CM_c that ignores the data input signals; and

means for determining a mathematical union of the clock models CM_i and CM_c for each mode i.