Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
First Claim
1. A method of vertically stacking wafers, comprising:
- selectively depositing a plurality of metallic lines on opposing surfaces of each of a first wafer and a second wafer;
bonding the first wafer to the second wafer by bonding the respective metallic lines on opposing surfaces of the first wafer and the second wafer to create a vertically stacked wafer pair;
forming one or more vias to establish electrical connections between the active devices on each wafer of the vertically stacked wafer pair and an external interconnect, the vias tapered from top to bottom hole, such that a top surface of each via has a larger area than a bottom surface; and
bonding two vertically stacked wafer pairs together by bonding the top surfaces of each of the one or more vias of a first vertically stacked wafer pair to corresponding top surfaces of each of the one or more vias of a second vertically stacked wafer pair.
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Accused Products
Abstract
A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
526 Citations
9 Claims
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1. A method of vertically stacking wafers, comprising:
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selectively depositing a plurality of metallic lines on opposing surfaces of each of a first wafer and a second wafer;
bonding the first wafer to the second wafer by bonding the respective metallic lines on opposing surfaces of the first wafer and the second wafer to create a vertically stacked wafer pair;
forming one or more vias to establish electrical connections between the active devices on each wafer of the vertically stacked wafer pair and an external interconnect, the vias tapered from top to bottom hole, such that a top surface of each via has a larger area than a bottom surface; and
bonding two vertically stacked wafer pairs together by bonding the top surfaces of each of the one or more vias of a first vertically stacked wafer pair to corresponding top surfaces of each of the one or more vias of a second vertically stacked wafer pair. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
selectively etching the top wafer to form a via;
depositing an oxide layer to insulate a sidewall of the via;
forming a barrier/seed layer in the via;
depositing a barrier layer in the via;
depositing a seed layer on the barrier layer; and
depositing a conduction metal on the seed layer in the via for providing an electrical connection between active devices on the vertically stacked wafers and the external interconnect.
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3. The method as claimed in claim 1, wherein the metallic lines are Copper (Cu) lines deposited to serve as electrical contacts between active devices on the vertically stacked wafers.
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4. The method as claimed in claim 2, wherein the conduction metal deposited in the via is copper (Cu) or a Cu alloy.
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5. The method as claimed in claim 2, wherein the barrier layer is comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and the Cu seed layer is comprised of a thin layer of copper (Cu) deposited on the barrier layer by chemical vapor deposition (CVD) process.
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6. The method as claimed in claim 1, further comprising dummy vias arranged on opposing surfaces of the adjacent wafers to increase the surface area for wafer-to-wafer bonding and serve as auxiliary structures for the active devices on the vertically stacked wafers.
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7. The method as claimed in claim 1, wherein each via is formed by a dual damascene process comprised of:
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selectively etching the top wafer to form an upper trench section of a via;
depositing an oxide layer to insulate a sidewall of the upper trench section of the via;
selectively etching the oxide layer in the upper trench section of the via to form a lower trench section of the via;
depositing a barrier layer in the via;
depositing a seed layer on the barrier layer; and
depositing a conduction metal on the seed layer for providing an electrical connection between active devices on the vertically stacked wafers and an external interconnect.
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8. The method as claimed in claim 7, wherein the barrier layer is comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and deposited in the upper trench section overlying the oxide layer and the lower trench section of the via;
- and the copper (Cu) seed layer is comprised of a thin layer of copper (Cu) deposited on the barrier layer deposited overlying the barrier layer in both the upper trench section and the lower trench section of the via.
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9. The method as claimed in claim 1, wherein the vias are formed during a Shallow Trench Isolation (IST) process in the top wafer before the adjacent wafers are bonded, via the respective metallic lines deposited on opposing surfaces of the adjacent wafers.
Specification