High Q inductor with faraday shield and dielectric well buried in substrate

• US 6,762,088 B2
• Filed: 01/03/2003
• Issued: 07/13/2004
• Est. Priority Date: 02/10/2001
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Rosner, Joanna, Cordes, Steven A., Lund, Jennifer L., Carasso, Melanie L., Acosta, Raul E., Groves, Robert A.
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US10/336,291
• Publication Number:
  US 20030096435A1
• Time in Patent Office: 557 Days
• Field of Search: 438/238, 438/381
• US Class Current: 438/238
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 27/36 Electric or magnetic shields or screens movable for varying inductance H01F21/10
• CPC Class Codes: H01F 27/363 made of electrically conductive material

Abstract

Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Claims

1. A method for making a conductive ground shield for use with an inductor in an integrated circuit, comprising:

a. providing a semiconductor substrate which is coated with a first passivation/insulation layer;

b. patterning in the first passivation/insulation layer and etching a well having walls and a floor through an area on the substrate which is preselected to be marginally larger than an inductor intended to be directly above the well;

c. covering the walls and floor of the well in turn with a second passivation/insulation layer, a conductor and a mask;

d. etching through the mask a ground shield having a connection to outside the well;

e. conformally applying a third passivation/insulation layer to the walls of the well and the etched ground shield; and

f. filling the well level with low-k dielectric material.

2. The method recited in claim 1, wherein the step of providing a semiconductor substrate comprises providing a substrate comprising Si, GaAs, HRS, quartz, sapphire, or SiGe.

3. The method recited in claim 1, wherein the step of providing a semiconductor substrate comprises providing an FEOL as a substrate.

4. The method recited in claim 1, wherein the passivation/insulation layers comprise SiO2, Si3N4 or BPSG.

5. The method recited in claim 1, wherein the step of etching a well having walls and a floor comprises etching a well having sloped walls and a floor using wet etching with an etchant selective to the substrate material.

6. The method recited in claim 5, wherein the step of using wet etching a well comprises using TMAH with a silicon substrate.

7. The method recited in claim 1, wherein the step of covering the walls and floor of the well with a conductor comprises covering the walls and floor of the well with a metal, doped silicon, doped polysilicon or silicide.

8. The method recited in claim 1, wherein the step of covering the walls and floor of the well with a mask comprises covering the walls and floor of the well with cured photoresist having continuity outside the well.

9. The method recited in claim 1, wherein the step of filling the well with low-k dielectric material comprises filling the well with a low-k cured polyimide.

10. A method of making an integrated inductor for a low loss IC, comprising performing the process steps recited in claim 1, and continuing process steps to complete the IC, including the step of fabricating an inductor directly vertically above the well.

11. The method recited in claim 10, wherein the well is filled with an organic dielectric and the step of continuing process steps to complete the IC and of fabricating an inductor includes the steps of etching between the turns of the inductor openings which extend down into the well, and removing the organic dielectric by reactive ion etching.