Chip structure and process for forming the same

• US 6,762,115 B2
• Filed: 04/16/2002
• Issued: 07/13/2004
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US10/125,226
• Publication Number:
  US 20020115282A1
• Time in Patent Office: 819 Days
• Field of Search: 438/598, 438/599, 438/618, 438/622, 438/624-629, 438/637, 438/648, 438/642-645, 438/650, 438/656, 438/652-654, 438/672, 438/680, 438/665-688, 438/106, 438/108, 438/113, 438/125, 438/126, 438/758, 438/761, 438/778, 438/759
• US Class Current: 438/598
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. The process for fabricating a chip structure, comprising:

Step 1;

providing a wafer having a plurality of electric devices, an interconnection scheme and a passivation layer, the interconnection scheme electrically connected to the electric devices, the passivation layer covering the electric devices and the interconnection scheme;

Step 2;

forming a dielectric sub-layer over the passivation layer of the wafer, the dielectric sub-layer having at least one opening passing through the dielectric sub-layer;

Step 3;

forming at least one conductive metal over the dielectric sub-layer and into the opening; and

Step 4;

removing the conductive metal formed outside the opening.

2. The process according to claim 1, wherein before Step 3 is performed, a conductive layer is formed on the dielectric sub-layer, and when Step 3 is performed, the conductive metal is formed on the conductive layer.

3. The process according to claim 1, wherein after Step 4, another dielectric sub-layer is formed over the passivation layer, and the another dielectric sub-layer covers the conductive metal.

4. The process according to claim 3, wherein after the another dielectric sub-layer is formed over the passivation layer, at least one node opening is formed through the another dielectric sub-layer and exposes the conductive metal.

5. The process according to claim 1, wherein the sequential steps 2-4 are repeated at least one time.

6. The process according to claim 5, wherein after Step 2 is performed each time, the opening of the dielectric sub-layer exposes the conductive metal formed over the passivation layer.

7. The process according to claim 5, wherein after the sequential steps 2-4 are repeated at least one time, another dielectric sub-layer is formed over the passivation layer, and the another dielectric sub-layer covers the top conductive metal.

8. The process according to claim 7, wherein after the another dielectric sub-layer is formed over the passivation layer, at least one node opening is formed through the another dielectric sub-layer and exposes the conductive metal.

9. The process according to claim 1, wherein the passivation layer having at least one opening exposing the interconnection scheme, further, during Step 2, the opening of the dielectric sub-layer exposes the opening of the passivation layer and the interconnection scheme exposed by the opening of the passivation layer.

10. The process according to claim 1, wherein during Step 3, a sputtering process, an electroplating process or both is used to form the conductive metal over the dielectric sub-layer and into the opening.

11. The process according to claim 1, wherein the material of the conductive metal includes titanium-tungsten alloy, titanium, chromium, aluminum, copper, nickel, or gold.

12. The process according to claim 1, wherein during Step 4, a chemical-mechanical polishing process is used to remove the conductive metal formed outside the opening.

13. The process for fabricating a chip structure, comprising:

Step 1;

providing a wafer having a plurality of electric devices, an interconnection scheme and a passivation layer, the interconnection scheme electrically connected to the electric devices, the passivation layer covering the electric devices and the interconnection scheme;

Step 2;

forming a first dielectric sub-layer over the passivation layer of the wafer, the first dielectric sub-layer having at least one via metal opening passing through the first dielectric sub-layer;

Step 3;

forming a first conductive layer onto the first dielectric sub-layer and into the via metal opening;

Step 4;

forming at least one first conductive metal over the first conductive layer;

Step 5;

removing the first conductive layer and the first conductive metal that are formed outside the via metal opening;

Step 6;

forming a second dielectric sub-layer onto the first dielectric sub-layer, the second dielectric sub-layer having at least one metal-layer opening passing through the second dielectric sub-layer, the metal-layer opening exposing the first conductive metal formed in the via metal opening;

Step 7;

forming a second conductive layer onto the second dielectric sub-layer and into the metal-layer opening;

Step 8;

forming at least one second conductive metal over the second conductive layer; and

Step 9;

removing the second conductive layer and the second conductive metal that are formed outside the metal-layer opening.

14. The process according to claim 13, wherein after Step 9, a third dielectric sub-layer is formed over the passivation layer, and the third dielectric sub-layer covers the second conductive metal.

15. The process according to claim 14, wherein after the third dielectric sub-layer is formed over the passivation layer, at least one node opening is formed through the third dielectric sub-layer and exposes the second conductive metal.

16. The process according to claim 13, wherein the sequential steps 2-9 are repeated at least one time.

17. The process according to claim 16, wherein after Step 2 is performed each time, the via metal opening exposes the second conductive metal formed over the passivation layer.

18. The process according to claim 16, wherein after the sequential steps 2-9 are repeated at least one time, a third dielectric sub-layer is formed over the passivation layer, and the third dielectric sub-layer covers the top second conductive metal.

19. The process according to claim 18, wherein after the third dielectric sub-layer is formed over the passivation layer, at least one node opening is formed through the third dielectric sub-layer and exposes the top second conductive metal.

20. The process according to claim 13, wherein the passivation layer having at least one opening exposing the interconnection scheme, further, during Step 2, the via metal opening exposing the opening of the passivation layer and the interconnection scheme exposed by the opening of the passivation layer.

21. The process according to claim 13, wherein during Step 3, a sputtering process is used to form the first conductive layer onto the first dielectric sub-layer and into the via metal opening.

22. The process according to claim 13, wherein during Step 4, a sputtering process or an electroplating process is used to form the first conductive metal over the first conductive layer.

23. The process according to claim 13, wherein during Step 5, a chemical-mechanical polishing process is used to remove the first conductive metal and the first conductive layer that are formed outside the via metal opening.

24. The process according to claim 13, wherein during Step 7, a sputtering process is used to form the second conductive layer onto the second dielectric sub-layer and into the metal-layer opening.

25. The process according to claim 13, wherein during Step 8, a sputtering process or an electroplating process is used to form the second conductive metal over the second conductive layer.

26. The process according to claim 13, wherein during Step 9, a chemical-mechanical polishing process is used to remove the second conductive metal and the second conductive layer that are formed outside the metal-layer opening.

27. The process according to claim 13, wherein the material of the first conductive layer includes titanium-tungsten alloy, titanium, chromium or aluminum.

28. The process according to claim 13, wherein the material of the first conductive metal includes aluminum, copper, nickel, or gold.

29. The process according to claim 13, wherein the material of the second conductive layer includes titanium-tungsten alloy, titanium or chromium or aluminum.

30. The process according to claim 13, wherein the material of the second conductive metal includes aluminum, copper, nickel, or gold.

31. A process for fabricating a chip structure, comprising:

Step 1;

providing a wafer having a plurality of electric devices, an interconnection scheme and a passivation layer, the interconnection scheme electrically connected to the electric devices, the passivation layer covering the electric devices and the interconnection scheme, the passivation layer having at least one opening exposing the interconnection scheme;

Step 2;

forming a dielectric sub-layer onto the passivation layer, the dielectric layer having at least one metal-layer opening passing through the dielectric sub-layer, the metal-layer opening exposing the opening of the passivation layer;

Step 3;

forming at least one conductive metal into the opening of the passivation layer, into the metal-layer opening and onto the dielectric sub-layer; and

Step 4;

removing the conductive metal that is formed outside the metal-layer opening and the opening of the passivation layer.

32. The process according to claim 31, wherein during Step 3, a sputtering process or an electroplating process is used to form the conductive metal into the opening of the passivation layer, into the metal-layer opening and onto the dielectric sub-layer.

33. The process according to claim 31, wherein during Step 4, a chemical-mechanical polishing process is used to remove the conductive metal that is formed outside the metal-layer opening.

34. The process according to claim 31, wherein the material of the first conductive layer includes titanium-tungsten alloy, titanium, chromium, aluminum, copper, nickel or gold.