MOSFET with SiGe source/drain regions and epitaxial gate dielectric
First Claim
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1. A semiconductor device formed on a substrate and comprising:
- a well, said well comprising two silicon germanium filled spaces and a remaining portion, said remaining portion of said well not comprising silicon germanium;
a channel region of first conductivity type and being in the well;
a dielectric layer overlying the channel region; and
a gate electrode overlying the dielectric layer;
wherein said two silicon germanium filled spaces comprise respective source/drain regions of second conductivity type, said respective source/drain regions being situated on opposite sides of the channel region.
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Abstract
In accordance with the invention, a MOSFET includes a well, a channel formed in the well, a high K layer overlying the channel, a buffer layer overlying the high k layer, a gate overlaying the buffer layer, a blocking layer overlying the gate and two source/drain regions. In some embodiments the gate and the source/drain regions are silicon germanium.
20 Citations
15 Claims
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1. A semiconductor device formed on a substrate and comprising:
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a well, said well comprising two silicon germanium filled spaces and a remaining portion, said remaining portion of said well not comprising silicon germanium;
a channel region of first conductivity type and being in the well;
a dielectric layer overlying the channel region; and
a gate electrode overlying the dielectric layer;
wherein said two silicon germanium filled spaces comprise respective source/drain regions of second conductivity type, said respective source/drain regions being situated on opposite sides of the channel region. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device formed on a substrate and comprising:
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a well;
a channel region of first conductivity type and being in said well;
a dielectric layer overlying said channel region;
a diffusion barrier layer overlying said dielectric layer;
a gate electrode overlying said diffusion barrier layer;
a blocking layer overlying said gate electrode; and
two source/drain regions of second conductivity type formed on opposite sides of said channel region;
wherein each of said dielectric layer, said diffusion barrier layer, and said blocking layer comprise epitaxial layers. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. A semiconductor device formed on a substrate and comprising:
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a well;
a channel region of first conductivity type and being in the well;
a dielectric layer overlying the channel region;
a diffusion barrier layer directly overlying and in contact with the dielectric layer, said diffusion barrier layer being a single layer;
a gate electrode directly overlying and in contact with the diffusion barrier layer, said gate electrode layer comprising a semiconductor material;
a blocking layer overlying the gate electrode;
two source/drain regions of second conductivity type formed on opposite sides of the channel region;
wherein each of the dielectric layer, the diffusion barrier layer, and the blocking layer comprise epitaxial layers.
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13. A semiconductor device formed on a substrate and comprising:
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a well;
a channel region of first conductivity type and being in the well;
a dielectric layer overlying the channel region;
a diffusion barrier layer directly overlying and in contact with the dielectric layer, said diffusion barrier layer being a single layer;
a gate electrode directly overlying and in contact with the diffusion barrier layer, said gate electrode layer comprising a semiconductor material;
a blocking layer overlying the gate electrode;
two source/drain regions of second conductivity type formed on opposite sides of the channel region;
wherein the gate electrode comprises silicon germanium.
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14. A semiconductor device formed on a substrate and comprising:
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a well;
a channel region of first conductivity type and being in the well;
a dielectric layer overlying the channel region;
a diffusion barrier layer directly overlying and in contact with the dielectric layer, said diffusion barrier layer being a single layer;
a gate electrode directly overlying and in contact with the diffusion barrier layer, said gate electrode layer comprising a semiconductor material;
a blocking layer overlying the gate electrode;
two source/drain regions of second conductivity type formed on opposite sides of the channel region;
wherein each of the source/drain regions comprises silicon germanium. - View Dependent Claims (15)
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Specification