Circuit for preserving data in a flip-flop and a method of use
First Claim
1. A flip-flop comprising:
- a first latch coupled to a first power supply; and
a second latch coupled to the first latch and coupled to a second power supply, wherein the first and second power supplies are independently controllable to minimize power consumption when the flip-flop is in a power saving mode; and
a state saving latch which is coupled to the second power supply and is only activated upon detection of standby power saving mode wherein the contents of the first latch are loaded into the state saving latch, wherein the first power supply is reduced to 0 volts and the second power supply is reduced to minimum voltage to sustain the state.
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Abstract
A method and a flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode. In a second aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.
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Citations
25 Claims
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1. A flip-flop comprising:
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a first latch coupled to a first power supply; and
a second latch coupled to the first latch and coupled to a second power supply, wherein the first and second power supplies are independently controllable to minimize power consumption when the flip-flop is in a power saving mode; and
a state saving latch which is coupled to the second power supply and is only activated upon detection of standby power saving mode wherein the contents of the first latch are loaded into the state saving latch, wherein the first power supply is reduced to 0 volts and the second power supply is reduced to minimum voltage to sustain the state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13)
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11. A flip-flop comprising:
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a first latch coupled to a first power supply, the first latch for receiving at least one bit;
a second latch coupled to the first latch and coupled to a second power supply, the second latch for storing the at least one bit from the first latch, wherein the size of the second latch is minimized to reduce power consumption;
a multiplexor coupled to the first latch and to the second latch for outputting the at least one bit from the first latch when a clock to the multiplexor is active and for outputting the at least one bit from the second latch when the clock is inactive, wherein the first and second power supplies are independently controllable; and
a state saving latch which is coupled to the second power supply and is only activated upon detection of standby power saving mode, wherein the contents of the first latch are loaded into the state saving latch, wherein the first power supply is reduced to 0 volts and the second power supply is reduced to minimum voltage to sustain the state. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A flip-flop comprising:
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a master latch adapted to be coupled to a first power supply, the master latch for receiving at least one bit; and
a slave latch coupled to the master latch and coupled to a second power supply, the slave latch for storing the at least one bit from the master latch wherein the size of the latch is minimized to reduce power consumption;
a shunt multiplexor coupled to the master latch and to the slave latch for outputting the at least one bit from the master latch when a clock to the multiplexor is active and for outputting the at least one bit from the slave latch when the clock is inactive, the voltage of the power supply coupled to the latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts; and
a state saving latch which is coupled to the second power and is only activated upon detection of standby power saving mode;
the voltage of the power supply coupled to the state saving latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts.- View Dependent Claims (20)
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21. A flip-flop comprising:
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a master latch coupled to a first power supply, the master latch for receiving at least one bit; and
a slave latch coupled to the master latch and coupled to a second power supply, the slave latch for storing the at least one bit from the master latch wherein the size of the latch is minimized to reduce power consumption;
a shunt multiplexor coupled to the master latch and to the slave latch for outputting the at least one bit from the master latch when a clock to the multiplexor is active and for outputting the at least one bit from the slave latch when the clock is inactive, the voltage of the power supply coupled to the latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts;
a restore mechanism which multiplexes a data and an output of the slave latch to enable recovery of the state of the contents of the master latch; and
a state saving latch which is coupled to the second power supply and is only activated upon detection of the power saving mode, the voltage of the power supply coupled to the state saving latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts.
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22. A method for minimizing the power consumption of a flip-flop, the flip-flop including a first latch and a second latch coupled thereto;
- the method comprising the steps of;
(a) providing a first independently controllable power supply coupled to the first latch;
(b) providing a second independently controllable power supply coupled to the second latch; and
(c) reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode wherein, in a power saving mode, the voltage of the power supply coupled to a state saving latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts. - View Dependent Claims (23, 24, 25)
- the method comprising the steps of;
Specification