Modified folded cascode amplifier

• US 6,762,646 B1
• Filed: 10/02/2002
• Issued: 07/13/2004
• Est. Priority Date: 10/02/2002
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Bell, Marshall J.
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US10/263,571
• Time in Patent Office: 650 Days
• Field of Search: 330/252, 330/253, 330/257, 330/292, 330/311
• US Class Current: 330/257
• CPC Class Codes: H03F 2203/45248 the dif amp being designed for improving the slew rate
• CPC Class Codes: H03F 2203/45264 the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45352 the AAC comprising a combination of a plurality of transistors, e.g. Darlington coupled transistors
• CPC Class Codes: H03F 2203/45512 the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45676 the LC comprising one cascode current mirror
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45744 by offset reduction

Abstract

A folded-cascode amplifier is arranged with a differential pair circuit, a current mirror circuit, and a cascode circuit. The differential pair is coupled to the current mirror circuit, while the cascode circuit is only coupled to one half of the current mirror circuit. A minimum number of transistors are employed such that overall speed is improved. An output stage with a compensation circuit may be coupled to an output of the cascode circuit. The cascode circuit is configured such that the compensation capacitor is driven with a current of approximately +/−2*I when slewing in the positive and negative directions.

Claims

1. An amplifier circuit, comprising:

a differential pair circuit that is arranged to steer a tail current between first and second nodes in response to a differential signal;

a current mirror circuit that is coupled to the first and second nodes, wherein the current mirror circuit is arranged to provide a reflected current to the second node when activated by at least a portion of the tail current, wherein the current mirror circuit includes;

a sixth transistor that is coupled to the first node, and a fifth transistor that is coupled to the second node, wherein the fifth and sixth transistors are commonly controlled by a signal from the first node; and

a cascode circuit that is biased by a cascode current, wherein the cascode circuit is coupled between a cascode output node and the second node such that second node is isolated from the cascode output node by the cascode circuit, wherein the amplifier is arranged to provide an output current to the cascode output node.

2. The amplifier circuit of claim 1, wherein the differential pair circuit includes a first current source that is arranged to provide the tail current, a first transistor that is arranged to steer the tail current to the first node in response to the differential signal, and a second transistor that is arranged to steer the tail current to the second node in response to the differential signal.

3. The amplifier circuit of claim 1, wherein the fifth and sixth transistors have associated sizes, and wherein the size associated with the fifth transistor is related to the size associated with the sixth transistor by a factor that is different from one.

4. The amplifier circuit of claim 1, wherein the current mirror circuit further includes a fourth transistor that is coupled between the first node and the sixth transistor, wherein the fourth transistor is arranged to reduce the voltage across the sixth transistor to minimize current reflection errors between the fifth and sixth transistors such that an offset associated with the amplifier is reduced.

5. The amplifier circuit of claim 1, wherein the cascode circuit further includes a second current source that is arranged to provide the cascode current, and a third transistor that is coupled between the cascode output node and the second node, wherein the third transistor is biased by a cascode bias signal.

8. The amplifier circuit of claim 1, further comprising an output stage that is arranged to provide an output signal at an output node in response to an input signal at the cascode output node.

9. The amplifier circuit of claim 8, further comprising a capacitor that is coupled between the second node and the output node, wherein the capacitor is arranged to reduce the gain of the amplifier at high frequencies.

10. The amplifier circuit of claim 8, further comprising a capacitor that is coupled between the second node and the output node, wherein the amplifier has a slew rate that is determined by a value associated with the capacitor, the tail current, and the cascode current.

6. An amplifier circuit, comprising:

a differential pair circuit that is arranged to steer a tail current between first and second nodes in response to a differential signal;

a current mirror circuit that is coupled to the first and second nodes, wherein the current mirror circuit is arranged to provide a reflected current to the second node when activated by at least a portion of the tail current, wherein the current mirror circuit includes a fourth transistor that is coupled between the first node and an input of the current mirror such that the current mirror circuit is cascoded; and

a cascode circuit that is biased by a cascode current, wherein the cascode circuit is coupled between a cascode output node and the second node such that second node is isolated from the cascode output node by the cascode circuit, wherein the amplifier is arranged to provide an output current to the cascode output node, wherein the cascode circuit further includes a second current source that is arranged to provide the cascode current, and a third transistor that is coupled between the cascode output node and the second node, wherein the third transistor is biased by a cascode bias signal, wherein the third and fourth transistors have associated sizes, and wherein the size associated with the third transistor is related to the size associated with the fourth transistor such that the third and fourth transistors operate with similar current densities.

7. An amplifier circuit, comprising:

a differential pair circuit that is arranged to steer a tail current between first and second nodes in response to a differential signal;

a current mirror circuit that is coupled to the first and second nodes, wherein the current mirror circuit is arranged to provide a reflected current to the second node when activated by at least a portion of the tail current; and

a cascode circuit that is biased by a cascode current, wherein the cascode circuit is coupled between a cascode output node and the second node such that second node is isolated from the cascode output node by the cascode circuit, wherein the amplifier is arranged to provide an output current to the cascode output node, wherein the cascode circuit further includes a second current source that is arranged to provide the cascode current, and a third transistor that is coupled between the cascode output node and the second node, wherein the third transistor is biased by a cascode bias signal, wherein the cascode circuit further includes a seventh transistor that is coupled between the second current source and the third transistor, wherein the seventh transistor is biased by another cascode bias signal such that the cascode output node is isolated from the second current source.

11. An amplifier circuit comprising:

a differential pair circuit that is arranged to steer a tail current between first and second nodes in response to a differential signal;

a current mirror circuit that is coupled to the first and second nodes, wherein the current mirror circuit is arranged to provide a reflected current to the second node when activated by at least a portion of the tail current;

a cascode circuit that is biased by a cascode current, wherein the cascode circuit is coupled between a cascode output node and the second node such that second node is isolated from the cascode output node by the cascode circuit, wherein the amplifier is arranged to provide an output current to the cascode output node;

an output stage that is arranged to provide an output signal at an output node in response to an input signal at the cascode output node; and

a capacitor that is coupled between the second node and the output node, wherein the amplifier has a slew rate that corresponds to +/−

2*I/C, wherein the tail current and the cascode current have a magnitude of I, and the capacitor has a value of C.

12. An apparatus comprising:

a differential pair circuit that includes a first current source that is coupled to a third node, a first transistor that is coupled between a first node and the third node, a second transistor that is coupled between a second node and the third node, wherein the first and second transistors are arranged to steer a tail current from the first current source to the first and second nodes in response to a differential signal;

a current mirror circuit that is coupled to the first and second nodes, wherein the current mirror circuit includes a fourth transistor that is coupled between the first node and a fourth node, a fifth transistor that is coupled to the first node and the second node, and a sixth transistor that is coupled to the first node and the fourth node, wherein the fifth and sixth transistor are commonly controlled by a signal from the first node such that a reflected current is provided to the second node when the sixth transistor is activated by at least a portion of the tail current; and

a cascode circuit that includes a second current source that is coupled to a fifth node, and a third transistor that is coupled between the fifth node and the second node, wherein the third transistor is biased by a cascode bias signal such that the amplifier is arranged to provide a cascode output current to the fifth node.

13. An apparatus as in claim 12, wherein the first current source is arranged to provide a tail current having a magnitude corresponding to I1, the second current source is arranged to provide a cascode current having a magnitude corresponding to I2, and wherein a the fifth and sixth transistors have associated sizes that are related to one another by a ratio that corresponds to:

1+2*(I2/I1).

14. The amplifier circuit of claim 13, wherein the second transistor is arranged to provide the tail current to the second node when the fifth transistor is deactivated, and the fifth transistor is arranged to conduct another current having a magnitude corresponding to I1+2*I2 when the second transistor is deactivated.

15. An apparatus as in claim 12, wherein the first current source is arranged to provide a tail current having a magnitude corresponding to I1, the second current source is arranged to provide a cascode current having a magnitude corresponding to I2, and wherein a the third and fourth transistors have associated sizes that are related to one another by a ratio that corresponds to:

2*(I2/I1).

16. An apparatus as in claim 12, further comprising an output stage that includes an eighth transistor that is coupled to the fifth node and an output node, wherein the eighth transistor is arranged to provide an output signal to the output node in response to signals at the fifth node.

17. The amplifier circuit of claim 16, further comprising a capacitor (C) that is coupled between the second node and the output node, wherein the first current source is arranged to provide a tail current having a magnitude corresponding to I1, and the second current source is arranged to provide a cascode current having a magnitude corresponding to I2 such that the amplifier charges capacitor C with a positive slew rate (SRP) corresponding to:

SRP=(I1+I2)/C.

18. The amplifier circuit of claim 16, further comprising a capacitor that is coupled between the second node and the output node, wherein the fifth transistor is ratioed in size to the sixth transistor according to a factor (X), the first current source is arranged to provide a tail current having a magnitude corresponding to I1, the second current source is arranged to provide a cascode current having a magnitude corresponding to I2, and transistor M1 has a parasitic capacitance (CP) that is coupled to node N3 such that the amplifier discharges capacitor C with a negative slew rate (SRN) corresponding to:

SRN=((X*I1)−

I2)/(C+CP).

19. The amplifier circuit of claim 17, wherein the value associated with the parasitic capacitance (CP) is much less than the value associated with the capacitor (C), such that the negative slew rate (SRN) corresponds to SRN=((X*I1)−

I2)/C.