Liquid crystal display device and fabrication method thereof

• US 6,762,802 B2
• Filed: 05/10/2001
• Issued: 07/13/2004
• Est. Priority Date: 05/12/2000
• Status: Expired due to Term

• Current Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ono, Kikuo, Oke, Ryutaro, Nakayoshi, Yoshiaki, Kaneko, Toshiki
• Primary Examiner(s): Kim, Robert H.
• Assistant Examiner(s): Duong, Thoi V.
• Application Number:
  US09/851,942
• Publication Number:
  US 20010040648A1
• Time in Patent Office: 1,160 Days
• Field of Search: 349/38, 349/43, 349/140, 349/158
• US Class Current: 349/38
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

The present invention provides a novel photolithography processes using photoresist pattern having at least two areas which has different thickness from each other for a fabrication method for a liquid crystal display device having reversed staggered and channel-etched type thin film transistors, reduce a number of photolithography processes required for whole of the fabrication process of the liquid crystal display device, and improve brightness of the liquid crystal display device.

Claims

1. A liquid crystal display device comprising:

a first insulating substrate and a second insulating substrate disposed to be opposite to the first insulating substrate;

a liquid crystal layer being interposed between the first insulating substrate and the second insulating substrate;

charges-holding capacitance sections, each of which has an upper electrode, a dielectric film and a lower electrode,

wherein said dielectric film is formed between said lower electrode and the upper electrode at each of said charges-holding capacitance sections, and said upper electrode contacts with said dielectric film through a contact hole provided by perforating a protective film formed over said dielectric film, and a semiconductor layer provided between said protective film and said dielectric film is selectively etched to be only around said contact hole.

2. A liquid crystal display device according to claim 1, wherein the semiconductor layer is formed around the contact hole on said dielectric film.

3. A liquid crystal display device according to claim 1, wherein said upper electrode is a pixel electrode.

4. A liquid crystal display device according to claim 1, further comprising:

a plurality of gate wiring lines, each of which is formed on the first insulating substrate and transmits a scanning signal;

a gate insulating film being formed on the first insulating substrate and the plurality of gate wiring lines;

a plurality of drain wiring lines, each of which is formed on the gate insulating film and transmits a video signal;

a plurality of semiconductor layers being formed on the gate insulating film and at least under one of the plurality of drain wiring lines;

thin film transistor sections, each of which has a semiconductor layer extended at least over a part of one of the plurality of gate wiring lines, a drain electrode formed of a part of the one of the plurality of drain wiring lines situated on said semiconductor layer, a source electrode formed on said semiconductor layer at an opposite side of the part of the one of the plurality of gate wiring liens to the drain electrode to be spaced from the drain electrode;

a protective film covering the plurality of drain wiring lines, the source electrodes, and the drain electrodes; and

a plurality of pixel electrodes, each of which is contacted with the source electrode of one of the thin film transistor sections,

wherein said dielectric film is a gate insulating film of said thin film transistor sections.