In-plane switching LCD with a redundancy structure for an opened common electrode and a high storage capacitance

• US 6,762,815 B2
• Filed: 12/12/2002
• Issued: 07/13/2004
• Est. Priority Date: 12/12/2002
• Status: Expired due to Fees

• Current Assignee: HannStar Display Corporation
• Original Assignee: HannStar Display Corporation
• Inventors: Lee, Deuk Su
• Primary Examiner(s): NGO, HUYEN LE
• Application Number:
  US10/317,525
• Publication Number:
  US 20040114082A1
• Time in Patent Office: 579 Days
• Field of Search: 349/38, 349/42, 349/141
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 2201/121 common or background

Abstract

An IPS-LCD array substrate has a redundancy structure for an opened common electrode line and a high storage capacitance. In each pixel unit area, a common electrode lines extends parallel to the signal line to overlap the signal line. A pixel electrode is parallel to the common electrode line. A common bus lines extends parallel to the gate line to overlap the gate line, and is electrically connected to the common electrode line. A complementary electrode pattern has a strip portion underneath and parallel to the pixel electrode, a bar portion parallel to the gate line and between the common bus line and the gate line, and an extension portion formed on the TFT and electrically connected to the pixel electrode. An insulator is sandwiched between the common electrode lines and the signal lines.

Claims

1. An IPS-LCD array substrate, comprising:

a plurality of gate lines and a plurality of signal lines perpendicularly arranged in a matrix form to define a plurality of pixels;

a plurality of TFTs formed in the plurality of pixels, respectively;

a redundancy pattern comprising a plurality of common electrode lines extending parallel to the signal lines and a plurality of common bus lines extending parallel to the gate lines, in which the common electrode lines overlap the signal lines respectively, the common bus lines overlap the gate lines respectively, and the common bus lines are electrically connected to the common electrode lines;

a plurality of pixel electrodes disposed parallel to the common electrode lines in the plurality of pixels, respectively;

a plurality of complementary electrode patterns formed in the plurality of pixels respectively; and

an insulator sandwiched between the common electrode lines and the signal lines;

wherein, the signal lines and the complementary electrode patterns are formed on the same plane, the common electrode lines, and the pixel electrodes and the common bus lines are patterned on the same plane.

2. The IPS-LCD array substrate according to claim 1, wherein each of the complementary electrode patterns comprises a strip portion underneath and parallel to the pixel electrode, a bar portion parallel to the gate line and between the common bus line and the gate line, and an extension portion formed on the TFT and electrically connected to the pixel electrode.

3. The IPS-LCD array substrate according to claim 1, further comprising:

a gate insulating layer covering the gate lines, wherein the signal lines and the complementary electrode patterns are patterned on the gate insulating layer.

4. The IPS-LCD array substrate according to claim 3, further comprising:

a passivation layer deposited on the gate insulating layer and covering the signal lines and the complementary electrode patterns, wherein the insulator is deposited on the passivation layer.

5. The IPS-LCD array substrate according to claim 1, wherein the TFT comprises:

a gate electrode protruded from the gate line;

a gate insulating layer deposited on the gate electrode,

a channel layer of a first semiconductor layer patterned on the gate insulating layer;

a source/drain diffusion region of a second semiconductor layer patterned on the channel layer; and

a source/drain electrode patterned on the source/drain diffusion region, respectively, in which a portion of the drain electrode is exposed by a via hole to form an electrical connection between the pixel electrode and the drain electrode;

wherein, the drain electrode is an extension of the signal line, the source electrode is an extension of the extension portion of the complementary electrode pattern, and the pixel electrode is electrically connected to the extension portion through the via hole.

6. The IPS-LCD array substrate according to claim 5, wherein the channel layer is an amorphous silicon (a-Si:

H) material, and the source/drain diffusion region is an n⁺-doped amorphous silicon (n⁺ a-Si;

H) material.

7. The IPS-LCD array substrate according to claim 1, wherein the signal lines and the complementary electrode patterns are formed by using a non-transparent conductive material.

8. The IPS-LCD array substrate according to claim 7, wherein the signal lines and the complementary electrode patterns are formed by using MoW or AlNd.

9. The IPS-LCD array substrate according to claim 1, wherein the common electrode lines, and the pixel electrodes and the common bus lines are formed by using a transparent conductive material.

10. The IPS-LCD array substrate according to claim 9, wherein the common electrode lines, and the pixel electrodes and the common bus lines are formed by using ITO or IZO.

11. An IPS-LCD, comprising:

a first substrate and a second substrate parallel to each other;

a liquid crystal layer disposed in a space between the first substrate and a second substrate;

a plurality of gate lines and a plurality of signal lines perpendicularly arranged in a matrix form on the first substrate to define a plurality of pixels;

a plurality of TFTs formed in the plurality of pixels, respectively;

a redundancy pattern comprising a plurality of common electrode lines extending parallel to the signal lines and a plurality of common bus lines extending parallel to the gate lines, in which the common electrode lines overlap the signal lines respectively, the common bus lines overlap the gate lines respectively, and the common bus lines are electrically connected to the common electrode lines;

a plurality of pixel electrodes disposed parallel to the common electrode lines in the plurality of pixels, respectively;

a plurality of complementary electrode patterns formed in the plurality of pixels respectively; and

an insulator sandwiched between the common electrode lines and the signal lines;

wherein, the signal lines and the complementary electrode patterns are formed on the same plane, the common electrode lines, and the pixel electrodes and the common bus lines are patterned on the same plane.

12. The IPS-LCD according to claim 11, wherein each of the complementary electrode patterns comprises a strip portion underneath and parallel to the pixel electrode, a bar portion parallel to the gate line and between the common bus line and the gate line, and an extension portion formed on the TFT and electrically connected to the pixel electrode.

13. The IPS-LCD according to claim 11, further comprising:

a gate insulating layer deposited on the first substrate and covering the gate lines, wherein the signal lines and the complementary electrode patterns are patterned on the gate insulating layer.

14. The IPS-LCD according to claim 13, further comprising:

a passivation layer deposited on the gate insulating layer and covering the signal lines and the complementary electrode patterns, wherein the insulator is deposited on the passivation layer.

15. The IPS-LCD according to claim 11, wherein the TFT comprises:

a gate electrode protruded from the gate line;

a gate insulating layer deposited on the gate electrode,

a channel layer of a first semiconductor layer patterned on the gate insulating layer;

a source/drain diffusion region of a second semiconductor layer patterned on the channel layer; and

a source/drain electrode patterned on the source/drain diffusion region, respectively, in which a portion of the drain electrode is exposed by a via hole to form an electrical connection between the pixel electrode and the drain electrode;

wherein, the drain electrode is an extension of the signal line, the source electrode is an extension of the extension portion of the complementary electrode pattern, and the pixel electrode is electrically connected to the extension portion through the via hole.

16. The IPS-LCD according to claim 15, wherein the channel layer is an amorphous silicon (a-Si:

H) material, and the source/drain diffusion region is an n⁺-doped amorphous silicon (n⁺ a-Si;

H) material.

17. The IPS-LCD according to claim 11, wherein the signal lines and the complementary electrode patterns are formed by using a non-transparent conductive material.

18. The IPS-LCD according to claim 17, wherein the signal lines and the complementary electrode patterns are formed by using MoW or AlNd.

19. The IPS-LCD according to claim 11, wherein the common electrode lines, and the pixel electrodes and the common bus lines are formed by using a transparent conductive material.

20. The IPS-LCD according to claim 19, wherein the common electrode lines, and the pixel electrodes and the common bus lines are formed by using ITO or IZO.