Low clock swing latch for dual-supply voltage design

• US 6,762,957 B2
• Filed: 12/20/2001
• Issued: 07/13/2004
• Est. Priority Date: 12/20/2001
• Status: Expired due to Term

• Current Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Original Assignee: Intel Corporation
• Inventors: Krishnamurthy, Ram K., Hsu, Steven K., Chatterjee, Bhaskar P.
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US10/027,795
• Publication Number:
  US 20030117933A1
• Time in Patent Office: 936 Days
• Field of Search: 365/189.05, 365/189.11, 365/227, 365/228, 365/189.06, 365/190, 326/28, 326/27, 326/26, 326/58, 326/57, 326/56, 326/81, 326/80
• US Class Current: 365/189.05
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

A dual-supply voltage latch includes a data input node to receive an input data, internal nodes to hold the input data, and an output node to output an output data. The latch also includes clock input nodes to receive a clock signal. The data input, internal, and data output nodes are at a higher potential than the clock nodes. Since clock nodes are high activity nodes, less potential on these nodes reduces the energy consumed by the latch. Although the data nodes and clock nodes are at different potentials, the latch has reduced static power dissipation.

Claims

1. A latch comprising:

an input circuit including a first and a second input switch connected together at a pulldown node, and a pulldown device connected between the pulldown node and a reference node;

a pullup circuit connected to the first input switch at a first internal node and to the second input switch at a second internal node; and

a feedback circuit including a first feedback switch connected to the first internal node and a second feedback switch connected to the second internal node, and an isolation device connected between the reference node and a node common to the first and second feedback switches.

2. The latch of claim 1, wherein the pullup circuit includes:

a first transistor having a drain and a source connected between the first internal node and a first supply node, and a gate connected to the second internal node; and

a second transistor having a drain and a source connected between the second internal node and the first supply node, and a gate connected to the first internal node.

3. The latch of claim 2, wherein the input circuit further includes an input inverter connected between a gate of the first input switch and a gate of the second input switch.

4. The latch of claim 3 further comprising:

an output buffer connected between one of the internal nodes and an output node.

5. The latch of claim 3 further comprising:

a data input node to receive a data signal, the data input node being connected to the gate of the first input switch; and

a clock input node to receive a clock signal, the clock input node being connected to a gate of the pulldown device.

6. The latch of claim 5 further comprising a clock inverter having an input connected to the clock input node, and an output connected to a gate of the isolation device.

7. The latch of claim 6, wherein the first input switch includes a drain connected to the first internal node and a gate connected to the data input node, wherein the second input switch includes a drain connected to the second internal node.

8. The latch of claim 7 further comprising a second supply node to receive a supply voltage different from a supply voltage received at the first supply node, the second supply node being connected to the clock inverter.

9. The latch of claim 7, wherein each of the data and clock signals has a first and a second potential level, wherein the first potential levels of the data and clock signals are the same and the second potential levels of the data and clock signals are unequal.

10. A latch comprising:

a first input transistor connected between a first internal node and a pulldown node;

a second input transistor connected between a second internal node and the pulldown node, and an input inverter connected between a gate of the first input transistor and a gate of the second input transistor;

a pulldown transistor connected between the pulldown node and a reference node;

a first pullup transistor connected between the first internal node and a first supply node;

a second pullup transistor connected between the second internal node and the first supply node; and

a feedback circuit including a first feedback transistor connected between the first internal node and a common node, a second feedback transistor connected between the second internal node and the common node, and a third feedback transistor connected between the common node and the reference node.

11. The latch of claim 10, wherein the first pullup transistor includes a gate connected to the second internal node, and the second pullup transistor includes a gate connected to the first internal node.

12. The latch of claim 11 further comprising:

a data input node to receive a data signal, the data input node being connected to a gate of the first input transistor; and

a clock input node to receive a clock signal, the clock node being connected to a gate of the pulldown transistor.

13. The latch of claim 12 further comprising a clock inverter having an input connected to the clock input node, and an output connected to a gate of the third feedback transistor.

14. The latch of claim 12 further comprising a second supply node to receive a supply voltage different from a supply voltage received at the first supply node, the second supply node being connected to the clock inverter.

15. The latch of claim 12, wherein each of data and clock signals has a first and a second potential level, wherein the first potential levels of the data and clock signals are the same and the second potential levels of the data and clock signals are unequal.

16. The latch of claim 10 further comprising:

an output buffer connected between one of the internal nodes and a latch-out node.

17. A latch comprising:

a clock path including a first and a second clock node to provide complementary clock signals;

a data path to receive a data signal, the data path including a first and a second input switch connected together at a pulldown node, and a pulldown device connected between the pulldown node and a reference node;

a pullup circuit connected to the first input switch at a first internal node and to the second input switch at a second internal node; and

a feedback circuit including a first stack of transistors connected to the first and second clock nodes and connected between the first and second internal nodes, and a second stack of transistors connected to the first and second clock nodes and connected between the first and second internal nodes.

18. The latch of claim 17, wherein first stack of transistors includes:

a first transistor having a gate connected to the first clock node; and

a second transistor having a gate connected to the second clock node, wherein the first and second transistors having their drains connected to one of the internal nodes.

19. The latch of claim 18, wherein the second stack of transistors includes:

a first transistor having a gate connected to the first clock node; and

a second transistor having a gate connected to the second clock node, wherein the first and second transistors of the second stack of transistors having their drains connected to the other of the internal nodes.

20. The latch of claim 19, wherein each of the first and second stacks of transistors includes third and fourth transistors having their gates connected to one of the internal nodes, wherein the first, second, third, and fourth transistors of each of the first and second stacks of transistors connects in series and in between a supply node and the reference node.

21. The latch of claim 20, wherein one of the complementary clock signals has a first and a second potential level and the data signal has a first and a second potential level, and wherein the first potential levels of the data signal and one of the clock signals are the same and the second potential levels of the data signal and one of the clock signals are unequal.

22. An integrated circuit comprising:

a first functional unit to output a data signal; and

a latch connected to the first functional unit, the latch including;

a clock path to receive a clock signal, the clock path being connected to a pulldown device;

a data path to receive the data signal to produce an output signal at an output node, the data path including a first transistor connected between a first internal node and the pulldown device, a second transistor connected between a second internal node and the pulldown device, and an inverter connected between one of the internal nodes and the output node;

a pullup circuit connected between a supply node and the first and second internal nodes; and

a feedback circuit including a first feedback transistor connected between the first internal node and a common node, a second feedback transistor connected between the second internal node and the common node, and a third feedback transistor connected to the common node and the clock path.

23. The integrated circuit of claim 22 further comprising a second functional unit connected to the latch to receive the output signal.

24. The integrated circuit of claim 23, wherein the clock path includes a second inverter connected between a gate of the pulldown device and a gate of the third feedback transistor.

25. The integrated circuit of claim 22, wherein the pullup circuit includes:

a first transistor having a source and a drain connected between the first internal node and the supply node, and a gate connected to the second internal node; and

a second transistor having a source and a drain connected between the second internal node and the supply node, and a gate connected to the first internal node.

26. The integrated circuit of claim 25, wherein each of data and clock signals has a first and a second potential level, wherein the first potential levels of the data and clock signals are the same and the second potential levels of the data and clock signals are unequal.

27. The integrated circuit of claim 22 further comprising a processor.