Generator/compactor scan circuit low power adapter with counter

• US 6,763,488 B2
• Filed: 03/09/2001
• Issued: 07/13/2004
• Est. Priority Date: 03/09/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US09/803,608
• Publication Number:
  US 20020112199A1
• Time in Patent Office: 1,222 Days
• Field of Search: 714/724, 714/726, 714/729, 714/741, 714/738
• US Class Current: 714/729
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318575 Power distribution; Power saving

Abstract

A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Claims

1. A scan circuit comprising:

A. a functional circuit formed on the semiconductor substrate of an integrated circuit, the functional circuit including logic circuits to be tested;

B. a scan path circuit formed of serially connected scan cells, the scan path circuit having leads connected to the logic circuits to carry stimulus signals to the logic circuits and to receive response signals from the logic circuits, the scan path circuit having a serial data input lead and a serial data output lead, the scan path circuit having control input leads for receiving control signals to control operation of the scan path circuit, the scan path circuit being organized in selectable, separate scan path parts, each scan path part having a serial input connected to the serial data input lead, a serial output lead selectively coupled to the serial data output lead and a separate set of control input leads;

C. a test data generator circuit having control inputs and a serial data output connected to the serial data input lead of the scan path circuit;

D. a test data compactor circuit having control inputs and a serial data input connected to the serial data output lead of the scan path circuit;

E. a controller having control output leads connected to the control inputs of the generator circuit and to the control inputs of the compactor circuit, and coupled to the control inputs of the scan path circuit; and

F. adaptor circuits coupling the control output leads of the controller to the separate sets of control input leads of the scan path circuit, the adaptor circuits including input leads receiving one set of control signals from the controller and including a set of output leads providing control signals for each scan path part, the adaptor circuits including a state machine controlling the production of the separate sets of control signals for operating the respective separate scan path parts, and the adaptor circuits including counter circuits connected to the state machine.

2. The circuit of claim 1 in which the state machine has counter control outputs and at least one count input, and the counter has control inputs connected to the counter control outputs and has at least one count output connected to the count input.

3. The circuit of claim 1 in which the scan path parts have equal numbers of scan cells and there is only one count input and one count output.

4. The circuit of claim 1 in which the scan paths have unequal numbers of scan cells and there are plural count outputs.

5. The circuit of claim 1 in which the state machine has a scan clock input, a scan enable input, an enable clock output for each scan path part, and an enable buffer output for each scan path part, the adaptor circuits including a gate for each scan path part, each gate having a first input connected to an enable clock output from the state machine and the scan clock input.