Method and apparatus for coordinating program execution in a site controller with pattern execution in a tester

• US 6,763,490 B1
• Filed: 09/25/2000
• Issued: 07/13/2004
• Est. Priority Date: 09/25/2000
• Status: Expired due to Fees

• Current Assignee: Verigy Limited (Advantest Corporation)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Krech, Alan S Jr., Freeseman, John M
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Trimmings, John P.
• Application Number:
  US09/669,262
• Time in Patent Office: 1,387 Days
• Field of Search: 714/738, 714/724, 714/718, 714/736, 714/743, 714/734, 714/32, 714/742, 714/744, 714/30, 714/31, 714/735, 714/25, 714/34, 714/33, 324/73.1, 324/158.1, 365/201, 365/230.03, 702/118, 716/4, 712/227, 712/245, 712/244
• US Class Current: 714/738
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A method and apparatus for coordinating program execution in a site controller with pattern execution in a tester executes the pattern in the tester and a pattern interruption instruction. The pattern interruption instruction causes the tester to write to a service request register in the site controller specifying a value that specifies a requested subroutine and a data source. The site controller initiates execution of the requested subroutine in the site controller using the specified data source.

Claims

1. A method of coordinating program execution in a site controller with test pattern execution in a tester comprising the steps of:

executing a test pattern in the tester,

executing a pattern interruption instruction in the tester,

the tester writing to a service request register in the site controller specifying a requested subroutine and a data source,

the site controller initiating execution of said requested subroutine in the site controller in response to a value in said service request register.

2. A method as recited in claim 1 and further comprising the step of the site controller alerting the tester of completion of the requested subroutine.

3. A method as recited in claim 2 further comprising the step of resuming execution of said test pattern after said step of alerting.

4. A method as recited in claim 3, said step of resuming further comprising the step of writing a trigger bit to a register.

5. A method as recited in claim 1, said step of executing the test pattern further comprising the steps of addressing a program instruction memory with a value in an address register, retrieving a program instruction from said program instruction memory, and generating a pattern vector from said program instruction, said method further comprising the step of generating a new value for said address register.

6. A method as recited in claim 3 wherein said step of executing said test pattern generates a pipeline of vectors for application to a device under test, the method further comprising the steps of continuing to execute said pipeline of vectors and preventing generation of additional vectors in said pattern.

7. A method as recited in claim 1 and further comprising the step of continuing execution of said pattern simultaneously with said step of initiating execution of said requested subroutine.

8. A method as recited in claim 1 further comprising the step of suspending execution of said pattern after said step of writing to said service request register.

9. A method as recited in claim 1 further comprising the step of restarting execution of a new test pattern.

10. A method as recited in claim 9, said step of restarting execution further comprising the step of writing a trigger bit to a register and a value to an address register.

11. A method as recited in claim 1 and further comprising the steps of checking for a value in a count register, sequentially modifying said count register if said count register does not reflect said value, and pausing said pattern execution if said count register reflects said value.

12. A method as recited in claim 11 wherein said value equals zero and said step of sequentially modifying said count register comprises decrementing said count register if said value in said count register is not equal to zero, and pausing said pattern execution if said value in said count register equals zero.

13. A method as recited in claim 12 and further comprising the steps of continuing administration of the test pattern to completion after said pattern interruption instruction and preventing application of vectors during said step of continuing administration.

14. An apparatus for coordinating program execution comprising

a site controller executing a routine,

a tester executing a test pattern,

a bus interconnecting said site controller and said tester,

a trigger register in said tester that initiates execution of said test pattern upon a write to said trigger register by said site controller, and

at least one service request register in said site controller having a value written by said tester that initiates and indicates to said site controller a requested subroutine for execution in said site controller.

15. An apparatus for coordinating program execution as recited in claim 14 wherein said at least one service request register specifies said subroutine from a plurality of available subroutines.

16. An apparatus for coordinating program execution as recited in claim 15 wherein said service request register also specifies a source of data for use by said subroutine.

17. An apparatus for coordinating program execution as recited in claim 16 wherein a second program register specifies a pointer into said source of said data for use by said subroutine.

18. An apparatus for coordinating program execution as recited in claim 17 and further comprising a scratch memory wherein said pointer specifies a location in said scratch memory as said source of said data for use by said subroutine.

19. An apparatus for coordinating program execution as recited in claim 14 and further comprising a second program register that specifies a data parameter for use by said subroutine.

20. An apparatus for coordinating program execution as recited in claim 14 and further comprising an address register in said tester having a value written by said site controller that points to a memory location in which said tester fetches a first instruction for execution of said pattern.

21. An apparatus for coordinating program execution as recited in claim 14 and further comprising a count register in said tester specifying a number of instructions to be executed by said tester.