Semiconductor wafer, semiconductor device, and method for manufacturing the same

• US 6,764,879 B2
• Filed: 07/24/2002
• Issued: 07/20/2004
• Est. Priority Date: 08/08/2001
• Status: Expired due to Term

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nagao, Koichi, Fujimoto, Hiroaki
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US10/200,950
• Publication Number:
  US 20030032263A1
• Time in Patent Office: 727 Days
• Field of Search: 438/110, 438/14, 438/15, 438/17, 257/777, 257/784
• US Class Current: 438/110
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor wafer of the present invention includes: a plurality of semiconductor chip areas each of which is to be a semiconductor chip; and a cut-off area for separating the plurality of semiconductor chip areas from one another so as to obtain the semiconductor chips, wherein: an integrated circuit and an electrode pad connected to the integrated circuit are provided in each of the semiconductor chip areas; and a probe pad connected to the electrode pad is provided in the cut-off area.

Claims

1. A semiconductor device, comprising:

a first semiconductor chip including a first integrated circuit, a first electrode pad connected to the first integrated circuit, and a first bump electrode formed on the first electrode pad;

a second semiconductor chip including a second integrated circuit, a second electrode pad connected to the second integrated circuit, and a second bump electrode formed on the second electrode pad, wherein;

a section of an inspection wire connected to the first electrode pad is exposed on a side surface of the first semiconductor chip; and

the first bump electrode and the second bump electrode are electrically connected to each other.

2. The semiconductor device of claim 1, wherein a probe pad is not provided in the first semiconductor chip.

3. The semiconductor device of claim 1, wherein an external electrode pad for connection to an external circuit is formed along a periphery of the second semiconductor chip.

4. The semiconductor device of claim 1, wherein an insulative resin is provided between the first semiconductor chip and the second semiconductor chip.

5. The semiconductor device of claim 1, wherein the first semiconductor chip and the second semiconductor chip are encapsulated by an encapsulation resin.

6. A method for manufacturing a semiconductor device, comprising the steps of:

(a) preparing a first semiconductor wafer, the first semiconductor wafer including;

a plurality of first semiconductor chip areas each of which is to be a first semiconductor chip; and

a cut-off area for separating the plurality of first semiconductor chip areas from one another so as to obtain the first semiconductor chips, wherein;

a first integrated circuit and a first electrode pad connected to the first integrated circuit are provided in each of the first semiconductor chip areas; and

a probe pad connected to the first electrode pad is provided in the cut-off area;

(b) inspecting each of the first semiconductor chips by contacting a probe to the probe pad;

(c) forming a first bump electrode on the first electrode pad;

(d) removing the cut-off area of the first semiconductor wafer so as to obtain the first semiconductor chips from the first semiconductor chip areas;

(e) preparing a second semiconductor wafer, the second semiconductor wafer including a plurality of second semiconductor chip areas each of which includes a second integrated circuit, and a second electrode pad connected to the second integrated circuit, and each of which is to be a second semiconductor chip;

(f) forming a second bump electrode on the second electrode pad formed in each of the second semiconductor chip areas;

(g) heating and pressing the first bump electrode and the second bump electrode against each other so as to electrically connect the first bump electrode and the second bump electrode to each other; and

(h) cutting the second semiconductor wafer so as to separate the second semiconductor chip areas from one another.

7. The method for manufacturing a semiconductor device of claim 6, wherein in the step (g), an insulative resin is supplied between the first semiconductor chip and the second semiconductor chip.

8. The method for manufacturing a semiconductor device of claim 6, wherein in the step (c) and the step (f), the first bump electrode and the second bump electrode are formed by using one of an electroplating method, an electroless plating method, a printing method, a dipping method, and a stud bump method.

9. The method for manufacturing a semiconductor device of claim 6, wherein in the step (c), the first bump electrode is made of one of an alloy containing tin and silver, an alloy containing tin and lead, tin, nickel, copper, indium, and gold.