Methods of forming vertical mosfets having trench-based gate electrodes within deeper trench-based source electrodes

• US 6,764,889 B2
• Filed: 07/17/2003
• Issued: 07/20/2004
• Est. Priority Date: 10/26/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Silicon Semiconductor Corporation
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Owens, Beth E.
• Application Number:
  US10/621,668
• Publication Number:
  US 20040016963A1
• Time in Patent Office: 369 Days
• Field of Search: 438/197, 438/212, 438/268, 438/270
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Methods of forming vertical MOSFETs include forming a base region of second conductivity type in a semiconductor substrate having a drift region of first conductivity type therein that forms a P-N junction with the base region. A source region of first conductivity type is formed in the base region and a deep trench, having a first sidewall that extends adjacent the base region, is formed in the substrate. The deep trench is lined with a first electrically insulating layer. The deep trench is then refilled with a trench-based source electrode. The trench-based source electrode is selectively etched to define a shallow trench therein and expose a first portion of the first electrically insulating layer that extends on the first sidewall of the deep trench. The first portion of the first electrically insulating layer is selectively etched to expose an upper portion of the first sidewall of the deep trench and reveal the base region. The shallow trench is lined with a gate insulating layer that extends on the exposed upper portion of the first sidewall of the deep trench and a bottom and sidewalls of the shallow trench. A gate electrode is formed in the lined shallow trench. A surface source electrode is also formed. This source electrode electrically connects the trench-based source electrode, source region and base region together.

Claims

1. A method of forming a vertical MOSFET, comprising the steps of:

forming a base region of second conductivity type in a semiconductor substrate having a drift region of first conductivity type therein that forms a P-N junction with the base region;

forming a source region of first conductivity type in the base region;

forming a deep trench having a sidewall that extends adjacent the base region, in the semiconductor substrate;

lining the deep trench with a an electrically insulating layer;

refilling the lined deep trench with a trench-based source electrode;

selectively etching the trench-based source electrode to define a shallow trench therein and expose a portion of the electrically insulating layer that extends on the sidewall of the deep trench;

selectively etching the portion of the electrically insulating layer to expose an upper portion of the sidewall of the deep trench and reveal the base region;

lining the shallow trench with a gate insulating layer that extends on the exposed upper portion of the sidewall of the deep trench and a bottom and sidewalls of the shallow trench;

forming a gate electrode that extends on a surface of the semiconductor substrate and extends into the lined shallow trench; and

forming a surface source electrode that electrically connects the trench-based source electrode, source region and base region together.

2. The method of claim 1, wherein said step of forming a surface source electrode is preceded by the steps of:

forming a blanket passivation layer on the semiconductor substrate; and

patterning the blanket passivation to define contact holes therein that expose the trench-based source electrode, source region and base region.

3. The method of claim 1, wherein the trench-based source electrode comprises polycrystalline silicon;

and wherein said step of lining the shallow trench comprises thermally oxidizing the exposed upper portion of the sidewall at a first rate and the bottom and sidewalls of the shallow trench at a second rate that is higher than the first rate.

4. The method of claim 3, wherein said thermally oxidizing step comprises thermally oxidizing an upper surface of the trench-based source electrode to define a surface oxide layer thereon;

and wherein said step of forming a surface source electrode is preceded by the step of selectively etching a portion of surface oxide layer extending adjacent the gate electrode to expose a portion of the upper surface of the trench-based source electrode.

5. The method of claim 1, wherein said step of lining the shallow trench comprises thermally oxidizing the exposed upper portion of the sidewall at a first rate and the bottom and sidewalls of the shallow trench at a second rate that is at least about equal to the first rate.

7. The method of claim 5, wherein said step of forming a surface source electrode is preceded by the steps of:

forming a blanket passivation layer on the semiconductor substrate; and

patterning the blanket passivation to define contact holes therein that expose the trench-based source electrode, source region and base region.

6. A method of forming a vertical MOSFET, comprising the steps of:

forming a semiconductor substrate having therein a drift region, a transition region on the drift region, a base region on the transition region and a source region on the base region;

forming a deep trench having a first sidewall that extends adjacent the base, transition and drift regions, in the semiconductor substrate;

forming a trench-based source electrode in the deep trench;

forming a shallow trench that exposes the base region and source region extending along the sidewall, in the trench-based source electrode;

forming a gate oxide insulating layer on the exposed base region;

forming a gate electrode that extends on an upper surface of the semiconductor substrate and extends into the shallow trench; and

forming a surface source electrode that electrically connects the trench-based source electrode, source region and base region together.

8. The method of claim 6, wherein said step of forming a gate electrode comprises forming multiple stripe-shaped gate electrodes that extend across the trench-based source electrode in a direction orthogonal to a lengthwise direction of the deep trench;

and wherein the surface source electrode electrically connects the trench-based source electrode, source region and base region at locations extending between the multiple stripe-shaped gate electrodes.

9. The method of claim 6, wherein the trench-based source electrode is separated from the sidewall by a an electrically insulating layer;

and wherein said step of forming a shallow trench comprises selectively etching a portion of the electrically insulating layer exposed by the shallow trench using the trench-based source electrode as an etching mask.