Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor

• US 6,764,901 B2
• Filed: 04/17/2000
• Issued: 07/20/2004
• Est. Priority Date: 10/06/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US09/551,027
• Publication Number:
  US 20020006699A1
• Time in Patent Office: 1,555 Days
• Field of Search: 438/243, 438/244, 438/248, 438/241, 438/268, 438/270, 438/587
• US Class Current: 438/243
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench

Abstract

A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Claims

1. A method of fabricating a memory array, the method comprising:

forming from a single unbonded substrate a number of access transistors separated by trenches, each access transistor formed in a pillar of semiconductor material that extends outwardly from the single unbonded substrate wherein each access transistor includes, in order, a first source/drain region, a body region and a second source/drain region formed vertically thereupon;

filling the trenches with a polysilicon layer, the polysilicon layer having a top surface below a top surface of the body region;

forming a nitride layer over the access transistors and the polysilicon layer;

removing first portion of the nitride layer and the entire polysilicon layer to form a plurality of bridges, each of the bridges including second portion of the nitride layer, each of the bridges extending through a column of access transistors;

forming a trench capacitor in the trenches, wherein a first plate of the trench capacitor is integral with the first source/drain region of the access transistor, wherein the trench capacitor is formed directly on the single unbonded substrate;

forming a number of word lines in the trenches that separate adjacent rows of access transistors, wherein each trench includes two word lines with a gate of each word line interconnecting alternate access transistors on opposite sides of the trench;

forming a number of bit lines that interconnect second source/drain regions of selected access transistors.

2. The method of claim 1, wherein forming a trench capacitor further includes forming a second plate that surrounds the first plate.

3. The method of claim 1, and further comprising forming a contact that couples a second plate of the trench capacitor to an underlying layer.

4. The method of claim 1, where forming a trench capacitor comprises forming a second plate that forms a grid pattern in a layer of material such that the grid surrounds each of the pillars that form the access transistors.

5. The method of claim 1, wherein forming a trench capacitor comprises depositing poly-silicon in crossing row and column isolation trenches formed around the pillars that define the access transistors.

6. The method of claim 1, wherein the memory array comprises memory cells each occupying an area of 4F2, wherein F is a minimum feature size.

7. The method of claim 1, wherein the first source/drain region is N+ doped.

8. The method of claim 7, including forming the first source/drain region to a thickness of approximately 3.5 micrometers.

9. The method of claim 7, wherein the body region is P−

doped.

10. The method of claim 9, including forming the body region by epitaxial growth of single-crystalline P−

silicon to a thickness of approximately 0.5 microns.

11. The method of claim 9, wherein the second source/drain region is N+ doped.

12. The method of claim 11, including forming the second source/drain region by implanting the N+ dopant to a depth of approximately 0.1 microns.

13. A method of fabricating a memory array, the method comprising:

epitaxially forming a first conductivity type first source/drain region layer on an unbonded substrate;

epitaxially forming a second conductivity type body region layer on the first source/drain region layer;

forming a first conductivity type second source/drain region layer on the body region layer;

forming a plurality of substantially parallel column isolation trenches extending through the second source/drain region layer, the body region layer, and the first source/drain region layer, thereby forming column bars between the column isolation trenches;

filling the column isolation trenches with a polysilicon layer, the polysilicon layer having a top surface below a top surface of the body region layer;

forming a nitride layer over the column bars and the polysilicon layer;

removing a first portion of the nitride layer and the entire polysilicon layer to form a plurality of substantially parallel row isolation trenches, orthogonal to the column isolation trenches, extending to substantially the same depth as the column isolation trenches, thereby forming an array of vertical access transistors for the memory array, wherein the removing the first portion of the nitride layer the entire polysilicon layer also forms a plurality of bridges orthogonal to the column isolation trenches, each of the bridges including a second portion of the nitride layer, each of the bridges extending through a column of vertical access transistors;

filling the row and column isolation trenches with a conductive material to a level that does not exceed the lower level of the body region so as to provide a common plate for capacitors of memory cells of the memory array, wherein the capacitors are formed directly on the unbonded substrate;

forming two conductive word lines in each row isolation trenches that selectively interconnect alternate vertical access transistors on opposite sides of the row isolation trench; and

forming bit lines that selectively interconnect the second source/drain regions of the vertical access transistors on each column.

14. The method of claim 13, wherein forming the first conductivity type source/drain region layer on the unbonded substrate comprises forming the first conductivity type first source/drain region layer outwardly from the unbonded substrate to a distance sufficient for the first source/drain region layer to also function as a first plate of the capacitor for each memory cell in the array.

15. The method of claim 13, wherein the memory array comprises memory cells each occupying an area of 4F2, wherein F is a minimum feature size.

16. The method of claim 13, wherein the first source/drain region is N+ doped.

17. The method of claim 13, including forming the first source/drain region to a thickness of approximately 3.5 micrometers.

18. The method of claim 13, wherein the unitary body region is P−

doped.

19. The method of claim 18, including forming the body region by epitaxial growth of single-crystalline P−

silicon to a thickness of approximately 0.5 microns.

20. The method of claim 18, wherein the second source/drain region is N+ doped.

21. The method of claim 20, including forming the second source/drain region by implanting the N+ dopant to a depth of approximately 0.1 microns.

22. A method of forming an array of memory cells, the method comprising:

forming using a single unbonded substrate a plurality of isolated vertical access transistors separated by trenches, the isolated vertical access transistors comprising in order outward from the single unbonded substrate, a first source drain region, a body region and a second source/drain region, wherein the separation of trenches is such that the area occupied by each memory cell is 4F2, wherein F is a minimum feature size;

filling the trenches with a polysilicon layer, the polysilicon layer having a top surface below a top surface of the body region;

forming a nitride layer over the isolated vertical access transistors and the polysilicon layer;

removing a first portion of the nitride layer and the entire polysilicon layer to form a plurality of bridges, each of the bridges including a second portion of the nitride layer, each of the bridges extending through a column of isolated vertical access transistors;

forming a trench capacitor for each memory cell, wherein a portion of the first source/drain region serves as a first plate of the capacitor, the trench capacitor is formed directly on the single unbonded substrate;

forming two word lines in select trenches, with a gate of each word line interconnecting alternate isolated vertical access transistors on opposite sides of the trench; and

forming bit lines that interconnect select second source/drain regions.

23. The method of claim 22, wherein the first source/drain region is N+ doped.

24. The method of claim 22 including forming the first source/drain region to a thickness of approximately 3.5 micrometers.

25. The method of claim 23, wherein the body region is P−

doped.

26. The method of claim 24, including forming the body region by epitaxial growth of single-crystalline P−

silicon to a thickness of approximately 0.5 microns.

27. The method of claim 25, wherein the second source/drain region is N+ doped.

28. The method of claim 27, including forming the second source/drain region by implanting the N+ dopant to a depth of approximately 0.1 microns.

29. The method of claim 22, wherein forming the trench capacitor further includes forming a second plate that surrounds the first plate.

31. A method according to claim 27, wherein the first conductivity type is N+ and the second conductivity type is P−

.

30. A method of forming an array of memory cells, the method comprising:

forming with a single unbonded substrate a first layer of a first conductivity type of single crystalline silicon, a second layer of a second conductivity type of single crystalline silicon, and a third layer of the first type of single crystalline silicon atop the second layer;

selectively etching through the third through first layers and partially into the single unbonded substrate so as to form a plurality of trenches and pillars spaced apart such that the surface area occupied by each memory cell is 4F2, wherein F is a minimum feature size;

filling the trenches with a polysilicon layer, the polysilicon layer having a top surface below a top surface of the second layer;

forming a nitride layer over the pillars and the polysilicon layer;

removing a first portion of the nitride layer and the entire polysilicon layer to form a plurality of bridges, each of the bridges including a second portion of the nitride layer, each of the bridges extending through a column of pillars;

filling the trenches with a conductive material so as to provide for a common plate for capacitors associated with each memory cell, such that a portion of the first layer in each pillar serves as a plate for the capacitor, wherein the capacitors are formed directly on the single unbonded substrate;

electrically interconnecting select pillars by word lines electrically coupled to the second layer of the select pillars, wherein each of the trenches includes two word lines; and

electrically interconnecting the select pillars by bit lines electrically coupled to the third layer of the select pillars.

32. A method of fabricating an array of memory cells, the method comprising:

forming, using a single unbonded substrate, spaced apart access transistors isolated by trenches, each access transistor comprising in order from the single unbonded substrate outward, an N+−

doped first source/drain region, a P−

doped body region and an N+−

doped second source/drain region;

filling the trenches with a polysilicon layer, the polysilicon layer having a top surface below a top surface of the body region;

forming a nitride layer over the access transistors and the polysilicon layer;

removing a first portion of the nitride layer and the entire polysilicon layer to form a plurality of bridges, each of the bridges including a second portion of the nitride layer, each of the bridges extending through a column of the access transistors;

forming capacitors in the trench corresponding to each access transistor, wherein a portion of the N+−

doped first source/drain region adjacent the single unbonded substrate serves as a plate for the capacitor corresponding to each access transistor, wherein the capacitors are formed directly on the single unbonded substrate; and

electrically connecting the access transistors in a manner that allows for an electrical charge to be accessed or stored in each capacitor via the corresponding access transistor, wherein each of the trenches includes two word lines selectively connected to the access transistors.

33. A method according to claim 32, wherein electrically connecting the access transistors includes:

forming a number of bit lines that interconnect second source/drain regions of selected access transistors.

34. A method of forming a memory device having an array of memory cells and a minimum feature size F, comprising:

forming using a single unbonded substrate a plurality of vertical access transistors separated by trenches and laid out in a substantially checker-board pattern such that the memory cells occupy an area of 4F2, wherein the formation of the vertical access transistors consists of forming a first source/drain region of a first dopant type, forming a body region of a second dopant type atop the first source/drain region, and forming a second source/drain region of a second dopant type atop the body region;

filling the trenches with a polysilicon layer, the polysilicon layer having a top surface below a top surface of the body region;

forming a nitride layer over the vertical access transistors and the polysilicon layer;

removing a first portion of the nitride layer and the entire polysilicon layer to form a plurality of bridges, each of the bridges including a second portion of the nitride layer, each of the bridges extending through a column of vertical access transistors;

forming a capacitor in the trenches by lining the trench with a gate oxide, and then filling the trench with polysilicon of the first type so as to surround a portion of the first source/drain region such that the surrounded portion of the first source/drain region serves as a first plate of the capacitor and the polysilicon in the trench serves as a second plate of the capacitor, wherein the capacitor is formed directly on the single unbonded substrate; and

electrically connecting the vertical access transistors via bit lines and word lines so as to provide the capability of accessing a charge stored in one or more of the capacitors or providing a charge thereto, wherein each of the trenches includes two word lines selectively connected to the vertical access transistors.

35. The method of claim 34, further including connecting the word lines to a word line decoder and the bit lines to a bit line decoder to provide selective access to the memory cells.

36. A method of forming an electronic device having an array of memory cells and a minimum feature size F, comprising:

forming with a single unbonded substrate a plurality of spaced apart access transistors each comprising in order outward from the single unbonded substrate, a first layer of N+ dopant serving as first source/drain, a second layer of P−

dopant serving as a body region and a third layer of N+ dopant serving as a second source/drain region;

wherein the forming of the access transistors includes forming trenches therebetween so as to provide a memory cell area of 4F2;

filling the trenches with a polysilicon layer, the polysilicon layer having a top surface below a top surface of the body region;

forming a nitride layer over the access transistors and the polysilicon layer;

removing a first portion of the nitride layer and the entire polysilicon layer to form a plurality of bridges, each of the bridges including a second portion of the nitride layer, each of the bridges extending through a column of access transistors;

forming, for each access transistor, a capacitor in the trenches by filling the trench with a thin layer of oxide and polysilicon, such that a portion of the first source/drain, the oxide layer and the polysilicon respectively serve as a first plate, a dielectric, and a second plate for the capacitor, wherein the capacitor is formed directly on the single unbonded substrate;

electrically connecting the access transistors with word lines and bit lines, wherein each of the trenches includes two word lines selectively connected to the access transistors;

connecting the word lines to a word line decoder;

connecting the bit lines to a bit line decoder;

operatively connecting the word line and bit line decoders to an address buffer; and

interfacing the address buffer to an electronic system via address lines.

37. The method of claim 36, wherein the electronic system is a microprocessor.

38. A method comprising:

growing a first layer over a substrate, the first layer including single crystalline silicon;

growing a middle layer over the first layer, the middle layer including single crystalline silicon;

growing a second layer over the middle layer, the second layer including single crystalline silicon;

depositing a pad layer over the second layer;

performing an etching process to form a plurality of parallel column trenches and a plurality of column bars interleaved with the column trenches, wherein the etching process includes etching the pad layer, etching the second layer, etching the middle layer, etching the first layer, and etching a portion of the substrate, and wherein each of the column bars includes a portion of the substrate, a portion of the first layer, a portion of the middle layer, a portion of the second layer, and a portion of the pad layer;

filling the column trenches with a polysilicon layer;

etching the polysilicon layer to a level below a top surface of the portion of the first layer in each of the column bars;

depositing a nitride layer over the column bars and the polysilicon layer;

planarizing the nitride layer to a level even with a surface of the portion of the pad layer of each of the column bars;

forming a photoresist layer over the nitride layer and the portion of the pad layer of each of the column bars, the photoresist layer having masked portion and openings, the each of the openings extending orthogonal to the column trenches;

etching the column bars, the nitride layer, and the polysilicon layer through the openings, wherein the etching exposes the polysilicon layer at the openings, and wherein the portion of the pad layer of each of the column bars under the masked portion and the nitride layer under the masked portion remain intact;

isotropically etching the polysilicon layer to form a plurality of row trenches orthogonal to the column trenches, a plurality of pillars arranged in column pillars parallel to the column trenches and arranged in rows pillars parallel to the row trenches, and a plurality bridges, each of the bridges connecting pillars in a column pillar, wherein each of the pillars includes a portion of the substrate, a first pillar portion formed by a part of the first layer, a middle pillar portion formed by a part of the middle layer, a second pillar portion formed by a part of the second layer, and a pad pillar portion formed by a part of the pad layer, wherein each of the bridges includes the nitride layer and the part of the pad layer in each pillar within a column pillar, and wherein each of the bridges has a bottom surface below a level of the top surface of the part of the first layer;

forming a dielectric on the substrate and on side walls of the first pillar portion of each of the pillars;

forming a conductive layer on the column trenches and the row trenches, wherein a surface of the conductive layer is at a level even with a level of the bottom surface of each of the bridges;

forming an insulation layer on the surface of the conductive layer;

forming an insulation layer on exposed side walls of each of the pillars, wherein the exposed side walls are side walls above the surface of the conductive layer;

forming at least one word line in each of the row trenches; and

forming a plurality of bit lines, each of the bit lines connecting the second pillar portion of each pillar in a column pillars.

39. A method comprising:

forming a first layer over a substrate, the first layer having a first conductivity type material;

forming a middle layer over the first layer, the middle layer having a second conductivity type material;

forming a second layer over the middle layer, the second layer having a first conductivity type material;

forming a first nitride layer over the second layer;

forming a plurality of parallel column trenches and a plurality of column bars interleaved with the column trenches;

forming a polysilicon layer in the column trenches, the polysilicon layer having a top surface below a top surface of the portion of the first layer in each of the column bars;

forming a second nitride layer over the column bars and the polysilicon layer, the second nitride layer having a top surface even with a top surface of the portion of the first nitride layer of each of the column bars;

removing a portion of the second nitride layer and the entire polysilicon layer to form a plurality of row trenches orthogonal to the column trenches, a plurality of pillars arranged in column pillars parallel to the column trenches and arranged in rows pillars parallel to the row trenches, and a plurality bridges, each of the bridges connecting pillars in a column pillar, wherein each of the pillars includes a portion of the substrate, a first pillar portion formed by a part of the first layer, a middle pillar portion formed by a part of the middle layer, a second pillar portion formed by a part of the second layer, and a nitride pillar portion formed by a part of the first nitride layer, wherein each of the bridges includes a top surface even with the top even with the top surface of the part of the first nitride layer of each of the pillars, and wherein each of the bridges includes a bottom surface below a level of the top surface of the part of the first layer of each of the pillars;

forming a dielectric on the substrate and on side walls of the first pillar portion of each of the pillars;

forming a conductive layer on the column trenches and the row trenches, wherein a surface of the conductive layer is at a level even with a level of the bottom surface of each of the bridges;

forming an insulation layer on the surface of the conductive layer;

forming an insulation layer on exposed side walls of each of the pillars, wherein the exposed side walls are side walls above the surface of the conductive layer;

forming a pair of word lines in each of the row trenches; and

forming a plurality of bit lines, each of the bit lines connecting the second pillar portion of each pillar in a column pillars.

40. A method comprising:

forming on a substrate a plurality of parallel column trenches and a plurality of column bars interleaved with the column trenches, wherein each of the column bars includes a portion of the substrate, a first layer, a middle layer, a second layer, and a pad layer;

forming a polysilicon layer in the column trenches, the polysilicon layer having a top surface below a top surface of the portion of the first layer in each of the column bars;

forming a nitride layer over the column bars and the polysilicon layer, the nitride layer having a top surface even with a top surface of the portion of the pad layer of each of the column bars;

removing a portion of the nitride layer the entire polysilicon layer to form a plurality of row trenches orthogonal to the column trenches, a plurality of pillars arranged in column pillars parallel to the column trenches and arranged in rows pillars parallel to the row trenches, and a plurality bridges, each of the bridges connecting pillars in a column pillar, wherein each of the pillars includes, a portion of the substrate, a the first pillar portion, formed by part of the first layer, a middle pillar portion formed by a part of the middle layer, a second pillar portion formed by a part of the second layer, and a pad portion formed by a part of the pad layer, wherein each of the bridges includes a top surface even with the top even with the top surface of the part of the pad layer of each of the pillars, and wherein each of the bridges includes a bottom surface below a level of the top surface of the part of the first layer of each of the pillars;

forming a dielectric on the substrate and on side walls of the first pillar portion of each of the pillars;

forming a conductive layer on the column trenches and the row trenches, wherein a surface of the conductive layer is at a level even with a level of the bottom surface of each of the bridges, wherein the first pillar portion, the middle pillar portion, and the second pillar portion form a source, a drain, and a body region of a vertical transistor, wherein the conductive layer and the first pillar portion of each of the pillars form a plurality of trench capacitors;

forming an insulation layer on the surface of the conductive layer;

forming an insulation layer on exposed side walls of each of the pillars, wherein the exposed side walls are side walls above the surface of the conductive layer;

forming a pair of word lines in each of the row trenches; and

forming a plurality of bit lines, each of the bit lines connecting the second pillar portion of each pillar in a column pillars.