Passivation of nitride spacer

• US 6,764,912 B1
• Filed: 08/02/2001
• Issued: 07/20/2004
• Est. Priority Date: 08/02/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Foster, John Clayton, Paton, Eric N., Buynoski, Matthew S., Xiang, Qi, Besser, Paul R., King, Paul L.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Toledo, Fernando L.
• Application Number:
  US09/919,943
• Time in Patent Office: 1,083 Days
• Field of Search: 438/229, 438/294, 438/296, 438/299, 438/301, 438/303, 438/304, 438/305, 438/306, 438/307, 438/655, 438/656, 438/657, 438/663, 438/664
• US Class Current: 438/305
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.

Claims

1. A method of passivating a silicon nitride spacer comprising the steps of:

providing a semiconductor substrate having a horizontal surface;

forming source and drain regions in the surface of the substrate;

forming a gate electrode on the horizontal surface of the substrate between said source and drain regions, said gate electrode having a horizontal top surface and sidewalls;

providing silicon nitride spacers on the sidewalls of the gate electrode;

depositing a layer of silicon oxide having a thickness of between 20 and 40 Å

over silicon nitride spacers and said horizontal surface of said semiconductor substrate and the horizontal top surface of said gate electrode;

removing the silicon oxide layer over said horizontal surface of said semiconductor substrate and the horizontal top surface of said gate electrode;

depositing nickel on said horizontal top surface of said gate and the horizontal surface of the substrate; and

annealing to react the nickel with silicon in the horizontal top surface of the gate electrode and in the horizontal surface of the substrate to form a metal silicide on said horizontal surfaces.

2. The method of claim 1, wherein said silicon oxide is formed by treating said substrate in a mixture of sulfuric acid and hydrogen peroxide.

3. The method of claim 1, wherein the gate dielectric is a dielectric selected from the group consisting of silicon dioxide, silicon oxynitride or a high-K dielectric.

4. The method of claim 1, where in the thickness of the silicon oxide layer is 20 Å

.

5. The method of claim 1, wherein the silicon oxide is removed using anisotropic sputter etching.

6. The method of claim 1, further including the step of removing the unreacted nickel.

7. A method of passivating a silicon nitride spacer comprising the steps of:

providing a semiconductor substrate having a horizontal surface;

forming source and drain regions in the surface of the substrate;

forming a gate electrode on the horizontal surface of the substrate between said source and drain regions, said gate electrode having a horizontal top surface and sidewalls;

providing silicon nitride spacers on the sidewalls of the gate electrode;

depositing a layer of silicon oxide having a thickness of between 20 and 40 Å

over silicon nitride spacers and said horizontal surface of said semiconductor substrate and the horizontal top surface of said gate electrode;

removing the silicon oxide layer over said horizontal surface of said semiconductor substrate and the horizontal top surface of said gate electrode;

depositing nickel on said horizontal top surface of said gate and the horizontal surface of the substrate;

annealing to react the nickel with silicon in the horizontal top surface of the gate electrode and in the horizontal surface of the substrate to form a metal silicide on said horizontal surfaces; and

wherein said silicon oxide is formed by treating said substrate in a mixture of sulfuric acid and hydrogen peroxide.

8. The method of claim 7, wherein the gate dielectric is a dielectric selected from the group consisting of silicon dioxide, silicon oxynitride or a high-K dielectric.

9. The method of claim 7, wherein the thickness of the silicon oxide layer is 20 Å

.

10. The method of claim 7, wherein the silicon oxide is removed using anisotropic sputter etching.

11. The method of claim 7, further including the step of removing the unreacted nickel.