Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric
First Claim
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1. A method of fabricating a semiconductor device formed on a semiconductor substrate having an active region, the method comprising the steps of:
- forming a gate dielectric layer on the semiconductor substrate;
forming a source and a drain within the active region of the semiconductor substrate;
forming a gate electrode on the gate dielectric layer wherein the gate electrode defines a channel interposed between the source and the drain; and
forming graded dielectric constant spacers on sidewalls of the gate electrode, sidewalls of the gate dielectric layer and portions of an upper surface of the semiconductor substrate, wherein the dielectric constant of the graded dielectric constant spacers decreases in value in a direction away from the gate dielectric layer.
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Abstract
A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.
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Citations
5 Claims
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1. A method of fabricating a semiconductor device formed on a semiconductor substrate having an active region, the method comprising the steps of:
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forming a gate dielectric layer on the semiconductor substrate;
forming a source and a drain within the active region of the semiconductor substrate;
forming a gate electrode on the gate dielectric layer wherein the gate electrode defines a channel interposed between the source and the drain; and
forming graded dielectric constant spacers on sidewalls of the gate electrode, sidewalls of the gate dielectric layer and portions of an upper surface of the semiconductor substrate, wherein the dielectric constant of the graded dielectric constant spacers decreases in value in a direction away from the gate dielectric layer. - View Dependent Claims (2, 3, 4, 5)
forming a first layer on the sidewalls of the gate electrode, the sidewalls of the gate dielectric and the portions of the upper surface of the semiconductor substrate;
forming a second layer on the first layer;
forming a third layer on the second layer; and
forming a fourth layer on the third layer, wherein the first layer has a dielectric constant greater than SiO2 and each of the second, third and fourth layers has a dielectric constant less than the dielectric constant of the preceding layer.
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3. The method of claim 2, further including the step of:
forming the first layer of one or more of Al2O3, HfO2, ZrO2, Ta2O5, BaTiO3, TiO2, CeO2, BST (Ba1−
xSrxO3), PZN (PbZnxNb1−
xO3) and PST (PbScxTa1−
xO3).
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4. The method of claim 3, further including the step of:
forming the second layer of one or more of SiO2, Si3N4, SiOxNy, Al2O3, HfO2, ZrO2, Ta2O5, BaTiO3, TiO2, CeO2, BST (Ba1−
xSrxO3), PZN (PbZnxNb1−
xO3) and PST (PbScxTa1−
xO3).
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5. The method of claim 4, further including the step of:
forming subsequent layers of one or more of SiO2, Si3N4, SiOxNy, Al2O3, HfO2, ZrO2, Ta2O5, BaTiO3, TiO2, CeO2, BST (Ba1−
xSrxO3), PZN (PbZnxNb1−
xO3) and PST (PbScxTa1−
xO3).
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Current AssigneeAdvanced Micro Devices, Inc.
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Original AssigneeAdvanced Micro Devices, Inc.
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InventorsNgo, Minh Van, Yang, Chih-Yuh, En, William George, Halliyal, Arvind, Lin, Ming-Ren
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Primary Examiner(s)GHYKA, ALEXANDER G
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Application NumberUS10/085,278Time in Patent Office874 DaysField of Search438/578, 438/582, 438/758, 438/785US Class Current438/785CPC Class CodesH01L 29/6656 using multiple spacer layer...H01L 29/66833 with a charge trapping gate...H01L 29/78 with field effect produced ...
