Device structure and method for reducing silicide encroachment

• US 6,765,273 B1
• Filed: 07/14/1998
• Issued: 07/20/2004
• Est. Priority Date: 06/30/1997
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tsai, Julie, Taylor, Mitch C., Chau, Robert S., Andideh, Ebrahim, Jan, Chia-Hong
• Primary Examiner(s): Tran, Thien F.
• Application Number:
  US09/115,405
• Time in Patent Office: 2,198 Days
• Field of Search: 257/412, 257/413, 257/388, 257/382, 257/384
• US Class Current: 257/412
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

Claims

1. A semiconductor device comprising:

an isolation region formed in a substrate, said isolation region having a top surface extending less than 1500 Å

above a substrate surface;

a silicon gate electrode formed on a gate dielectric formed on said substrate surface, said silicon gate electrode having a first thickness;

a gate silicide layer formed on said silicon gate electrode, said gate silicide layer having a second thickness, said second thickness greater than said first thickness;

a pair of sidewall spacers on opposite sides of said gate electrode, said sidewall spacers having a height of at least 200Å

above the second thickness of the gate silicide layer, and said sidewall spacers each having a width less than 300Å

;

a pair of source/drain regions formed on opposite sides of said silicon gate electrode; and

a source/drain silicide layer formed on said source/drain regions, said source/drain silicide layer having said second thickness and wherein the top surface of said source/drain silicide layer has a height less than the top surface of said isolation region.

2. The semiconductor device of claim 1, wherein said silicon gate electrode is polysilicon.

3. The semiconductor device of claim 1 wherein said isolation region is a shallow trench isolation region.