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Membrane 3D IC fabrication

  • US 6,765,279 B2
  • Filed: 02/05/2001
  • Issued: 07/20/2004
  • Est. Priority Date: 04/08/1992
  • Status: Expired due to Term
First Claim
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1. Circuitry comprising:

  • a first integrated circuit;

    a second integrated circuit that is thinned, wherein the thickness of the second integrated circuit is less than about 50 microns and the second integrated circuit having a dielectric layer with a dielectric stress of less than about 8×

    108 dynes/cm2; and

    a compression bond formed between the first and second integrated circuits, wherein the compression bond provides a primary means of adhesion between the first and second integrated circuits.

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