Semiconductor structure and method for determining critical dimensions and overlay error

• US 6,765,282 B2
• Filed: 04/29/2002
• Issued: 07/20/2004
• Est. Priority Date: 08/30/2001
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schulz, Bernd
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): GREENE, PERSHELLE L
• Application Number:
  US10/134,564
• Publication Number:
  US 20030042579A1
• Time in Patent Office: 813 Days
• Field of Search: 257/629, 257/632, 257/635, 257/636, 356/445, 356/376, 356/351, 356/357, 356/388, 356/237.1, 356/3, 356/630, 356/631, 356/632, 356/625, 356/601, 356/622, 356/399, 356/400, 356/401, 356/369, 430/30, 438/14
• US Class Current: 257/629
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure and a method of determining an overlay error produced during formation of the semiconductor structure are disclosed. The semiconductor structure comprises a first two-dimensional periodic pattern and a second two-dimensional periodic pattern, which overlap with each other, wherein a relative position between the overlapping first and second two-dimensional periodic patterns indicates the magnitude and direction of an overlay error caused during the formation of the first and second two-dimensional periodic patterns. The semiconductor allows one to independently determine the overlay errors in linearly independent directions by directing a light beam of known optical properties onto the first and second two-dimensional periodic patterns and by analyzing the diffracted beam by comparison with reference data.

Claims

1. A semiconductor structure for metrology of critical dimensions and overlay accuracy, comprising:

a substrate having a surface defined by an X-direction and a Y-direction;

a first periodic pattern formed on the substrate and having a first X-periodicity along the X-direction and a first Y-periodicity along the Y-direction; and

a second periodic pattern formed on the substrate and having a second X-periodicity along the X-direction and a second Y-periodicity along the Y-direction;

wherein the first periodic pattern and the second periodic pattern overlap with each other to define an X-overlap region indicating an overlay error in the X-direction, and a Y-overlap region indicating an overlay error in the Y-direction.

2. The semiconductor structure of claim 1, wherein the first X-periodicity is defined by a first X-grating and the first Y-periodicity is defined by a first Y-grating.

3. The semiconductor structure of claim 1, wherein the first X-grating and the first Y-grating comprise lines and spaces extending along the X- and Y-directions, respectively.

4. The semiconductor structure of claim 2, wherein the first X-grating is formed by adjacent lines of different optical properties, and the first Y-grating is formed by adjacent lines of different optical properties.

5. The semiconductor structure of claim 4, wherein two adjacent lines of the X-grating and of the Y-grating are formed of a different material.

6. The semiconductor structure of claim 2, wherein the first X-periodicity is defined by adjacent first and second regions, wherein the first and second regions differ from each other in at least one of a shape, a type of material and a surface profile.

7. The semiconductor structure of claim 2, wherein the first Y-periodicity is defined by adjacent first and second regions, wherein the first and second regions differ from each other in at least one of a shape, a type of material and a surface profile.

8. The semiconductor structure of claim 1, wherein the second periodic pattern comprises first line portions and second line portions that are oriented in one of the X-direction and the Y-direction.

9. The semiconductor structure of claim 8, wherein the first line portions form a part of said X-overlap region for a predefined range of X-overlay errors, and wherein the second line portions form a part of said Y-overlap region for a predefined interval of Y-overlay errors.

10. The semiconductor structure of claim 5, wherein the second periodic pattern is a second grating.

11. The semiconductor structure of claim 10, wherein the first and second periodic patterns define a plurality of elementary cells, whereby each elementary cell comprises N first line portions, where N is an integer number equal or larger than 1.

12. The semiconductor structure of claim 11, wherein each elementary cell comprises at least one second line portions having a predefined length L, with L being smaller than a length of the first line portions.

13. The semiconductor structure of claim 12, wherein a ratio of N and L is selected to adjust the response of the first and second periodic patterns.

14. A semiconductor structure for metrology of critical dimensions and overlay accuracy, comprising:

a substrate having a surface defined by an X-direction and a Y-direction;

a two-dimensional periodic structure including a plurality of elementary cells, each elementary cell comprising;

a first region and a second region that define a first edge extending along the X-direction, and a second edge extending along the Y-direction; and

a third region formed in spaced relationship to the first and second regions, the third region defining a Y overlap region with the first and second regions at the first edge, and defining an X overlap region with the first and second regions at the second edge, wherein the X overlap region and the Y overlap region differ from each other in at least one of a shape, a total area, a diffracting characteristic, and an optical characteristic.

15. The semiconductor structure of claim 14, wherein at least one of the characteristics from the group of shape, total area, diffracting characteristics and optical characteristics of the X-overlap region is determined by an overlay error in the X-direction, and wherein at least one of the characteristics from the group of shape, total area, diffracting characteristics, and optical characteristics of the Y overlap region is determined by an overlay error in the Y-direction.

16. The semiconductor structure of claim 14, wherein at least one of the first, second and third regions comprises one or more recessed regions.

17. The semiconductor structure of claim 16, wherein said one or more recessed regions are openings.

18. The semiconductor structure of claim 14, wherein the third region is formed over the first and second regions.

19. The semiconductor structure of claim 14, further comprising a fourth region formed in the same material layer as the third region.

20. A semiconductor structure for metrology of critical dimensions and overlay accuracy comprising:

a substrate having a surface defined by an X-direction and a Y-direction;

a first periodic pattern formed above the substrate; and

a second periodic pattern formed above the substrate;

wherein the first and second periodic patterns overlap with each other and define a composed two-dimensional diffracting pattern having a pitch DX along the X-direction and a pitch DY along the Y-direction, DX and DY being determined by the relative position of the first and second periodic patterns.

21. The semiconductor structure of claim 20, wherein the first and second periodic patterns are formed in a first material layer and a second material layer, respectively.

22. The semiconductor structure of claim 21, wherein the first periodic pattern and the second periodic pattern are spaced apart along the X-direction by a distance determined by an overlay error between the first and the second material layer.

23. The semiconductor structure of claim 22, wherein the first and second periodic patterns are spaced apart along the Y-direction by a distance determined by an overlay error along the Y-direction.