Semiconductor device and the method for manufacturing the same

• US 6,765,299 B2
• Filed: 03/05/2001
• Issued: 07/20/2004
• Est. Priority Date: 03/09/2000
• Status: Expired due to Term

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Takahashi, Yoshikazu, Ohsumi, Takashi
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Rose, Kusha
• Application Number:
  US09/797,907
• Publication Number:
  US 20010038151A1
• Time in Patent Office: 1,233 Days
• Field of Search: 257/777, 257/688, 257/778, 257/774, 438/637, 438/108
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device includes a first semiconductor chip having a plurality of pads, a second semiconductor chip having a plurality of pads, the second semiconductor chip being fixed over a main surface of the first semiconductor chip, an insulating layer formed between the first semiconductor chip and the second semiconductor chip a plurality of conductive posts formed over the main surface of the first semiconductor chip and a main surface of the second semiconductor chip, the plurality of conductive posts being electrically connected to the plurality of pads on the first semiconductor chip and the plurality of pads on the second semiconductor chip and a resin covering the main surfaces of the first and second semiconductor chips, the resin partially covering the plurality of conductive posts.

Claims

1. A semiconductor device comprising:

a first semiconductor chip having a main surface, the main surface including a plurality of pads;

an insulating layer formed on the main surface of said first semiconductor chip;

a second semiconductor chip having a plurality of pads, said second semiconductor chip being fixed on said insulating layer over the main surface of said first semiconductor chip;

a plurality of conductive posts formed over the main surface of said first semiconductor chip on said insulating layer and over a main surface of said second semiconductor chip, said plurality of conductive posts being electrically connected to the plurality of pads on said first semiconductor chip and the plurality of pads on said second semiconductor chip; and

a resin covering said insulating layer and the main surfaces of said first and second semiconductor chips, said resin partially covering said plurality of conductive posts.

2. The semiconductor device as claimed in claim 1, further comprising:

a conductive layer formed under a back surface of said second semiconductor chip, said conductive layer electrically connecting the back surface of said second semiconductor chip to one of said plurality of conductive posts.

3. The semiconductor device as claimed in claim 1, further comprising:

an insulating side wall structure formed on a side surface of said second semiconductor chip; and

a conductive layer formed over said insulating side wall structure, electrically connecting one of said plurality of pads formed on said first semiconductor chip to one of said plurality of pads formed on said second semiconductor chip.

4. The semiconductor device as claimed in claim 1, further comprising interconnections formed on said insulating layer that electrically connect said plurality of conductive posts to the plurality of pads on said first semiconductor chip.

5. The semiconductor device as claimed in claim 4, wherein the interconnections are formed through said insulating layer to electrically contact the plurality of pads on said first semiconductor chip.

6. The semiconductor device as claimed in claim 1, wherein said second semiconductor chip is fixed on said insulating layer by a die bonding material.

7. The semiconductor device as claimed in claim 1, wherein said insulating layer comprises a polymide layer on a silicon oxide layer.

8. A semiconductor device comprising:

a first semiconductor chip having a main surface, the main surface including a plurality of pads;

a second semiconductor chip having a plurality of pads, said second semiconductor chip being fixed over the main surface of said first semiconductor chip;

an insulating layer formed on the main surface of said first semiconductor chip, said insulating layer having a thickness greater than a thickness of said second semiconductor chip and having a concave portion, said second semiconductor chip being set in the concave portion;

a plurality of conductive posts formed over the main surface of said first semiconductor chip on said insulating layer and over a main surface of said second semiconductor chip, said plurality of conductive posts being electrically connected to the plurality of pads on said first semiconductor chip and the plurality of pads on said second semiconductor chip; and

a resin covering said insulating layer and the main surfaces of said first and second semiconductor chips, said resin partially covering said plurality of conductive posts.

9. The semiconductor device as claimed in claim 8, further comprising interconnections formed on said insulating layer that electrically connect said plurality of conductive posts to the plurality of pads on said first semiconductor chip.

10. The semiconductor device as claimed in claim 9, wherein the interconnections are formed through said insulating layer to electrically contact the plurality of pads on said first semiconductor chip.

11. The semiconductor device as claimed in claim 8, wherein said second semiconductor chip is fixed on said insulating layer by a die bonding material.

12. The semiconductor device as claimed in claim 8, wherein said insulating layer comprises a polymide layer on a silicon oxide layer.

13. A semiconductor device comprising:

a first semiconductor chip having a main surface, the main surface including a plurality of pads;

a second semiconductor chip having a main surface including a plurality of pads, said second semiconductor chip being fixed over the main surface of said first semiconductor chip, the main surface of said first semiconductor chip facing the main surface of said second semiconductor chip;

a plurality of conductive posts formed over the main surface of said first semiconductor chip and electrically connected to the plurality of pads on said first semiconductor chip;

a plurality of conductive electrodes formed on the plurality of pads of said second semiconductor chip and electrically connected to the plurality of pads on said first semiconductor chip;

a resin covering the main surface of said first semiconductor chip and a back surface of said second semiconductor chip, said resin partially covering said plurality of conductive posts; and

an insulating layer formed on the main surface of a said first semiconductor chip,

said second semiconductor chip and said plurality of conductive posts being formed on said insulating layer over the main surface of said first semiconductor chip.

14. The semiconductor device as claimed in claim 13, further comprising:

a via-hole formed through said second semiconductor chip;

a conductive material formed in said via-hole, said conductive material electrically connected to the plurality of pads on said second semiconductor chip; and

a plurality of interconnections formed over the back surface of said second semiconductor chip, at least one of said plurality of interconnections electrically connected to said conductive material in said via-hole.

15. The semiconductor device as claimed in claim 13, further comprising:

a conductive layer formed on said insulating layer over said first semiconductor chip, electrically connecting one of said plurality of pads formed on said first semiconductor chip to one of said plurality of pads formed on said second semiconductor chip.

16. The semiconductor device as claimed in claim 13, further comprising interconnections formed on said insulating layer that electrically connect said plurality of conductive posts to the plurality of pads on said first semiconductor chip.

17. The semiconductor device as claimed in claim 16, wherein the interconnections are formed through said insulating layer to electrically contact the plurality of pads on said first semiconductor chip.

18. The semiconductor device as claimed in claim 13, wherein said insulating layer comprises a polymide layer on a silicon oxide layer.