Low drop-out regulator and an pole-zero cancellation method for the same

• US 6,765,374 B1
• Filed: 07/10/2003
• Issued: 07/20/2004
• Est. Priority Date: 07/10/2003
• Status: Expired due to Fees

• Current Assignee: Fairchild Corporation (ON Semiconductor Corporation)
• Original Assignee: System General Corporation (ON Semiconductor Corporation)
• Inventors: Yang, Ta-yung, Chen, Chern-Lin, Pan, Hsuan-I, Lin, Jenn-yu G.
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US10/617,951
• Time in Patent Office: 376 Days
• Field of Search: 323/273, 323/280, 323/281, 323/349
• US Class Current: 323/280
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A method an apparatus to dynamically modify the internal compensation of a low drop-out (LDO) linear voltage regulator is presented. The process involves creating an additional equivalent series resistance (ESR) from an internal circuit. The additional ESR of the internal circuit is sufficient to ensure DC output stability. This allows the ESR of the output capacitance to be reduced to zero if desired, for improved transient response. The zero induced by the ESR of the internal circuit is frequency compensated, so that it tracks the position of the output pole as the load varies.

Claims

1. A low drop-out voltage regulator having an adaptive frequency compensation means, comprising:

a regulated DC output terminal;

an unregulated DC input terminal;

an output section having an output capacitor and an output load, wherein said output load is connected from said regulated DC output terminal to the ground reference, and said output capacitor is connected in parallel to a said output load;

an output pass element for supplying power to said output section, wherein said output pass element having a source is coupled to said unregulated DC input terminal, and said output pass element having a drain is connected to said regulated DC output terminal;

a control circuit for controlling a gate of said output pass element;

a stabilizing-zero resistor for generating a zero;

wherein said stabilizing-zero resistor generates an additional equivalent series resistance (ESR); and

a pole-zero tracking circuit for controlling a frequency of said zero.

2. The low drop-out voltage regulator according to claim 1, wherein said control circuit comprises:

an error amplifier for generating a gate signal, wherein said error amplifier has a negative input connected to a reference voltage port;

an AC feedback terminal for supplying a high-frequency feedback signal to said error amplifier;

a blocking capacitor for blocking DC components from said AC feedback terminal, wherein said blocking capacitor is connected between a positive input of said error amplifier and said AC feedback terminal;

a feedback transistor for supplying a feedback current to said AC feedback terminal, wherein said feedback current is proportional to an output current of the output section, said feedback transistor has a source coupled to the unregulated DC input terminal, and said feedback transistor has a drain coupled to said AC feedback terminal;

a DC feedback terminal for supplying a steady-state feedback signal to said error amplifier, wherein said DC feedback terminal is connected to said regulated DC output terminal; and

a large-resistance resistor for maintaining the DC accuracy of the feedback signal, wherein said large-resistance resistor is connected between said DC feedback terminal and the positive input of said error amplifier, and said large-resistance resistor is a device with an equivalent resistance of 10 MΩ

or more.

3. The low drop-out voltage regulator according to claim 1, wherein said stabilizing-zero resistor is connected between said regulated DC output terminal and said AC feedback terminal.

4. The low drop-out voltage regulator according to claim 1, wherein said pole-zero tracking circuit comprises:

a switch for modulating the frequency of the zero; and

a pole-zero tracking transistor for increasing the throughput of the feedback current, wherein said pole-zero tracking transistor has a source connected the unregulated DC input terminal, and said pole-zero tracking transistor has a drain connected to said AC feedback terminal via said switch.

5. The low drop-out voltage regulator according to claim 1, wherein a frequency of the zero decreases whenever the switch is closed.

6. The low drop-out voltage regulator according to claim 1, wherein a frequency of the zero increases whenever the switch is opened.

7. The low drop-out voltage regulator according to claim 1, wherein a common gate signal is supplied by an output of said error amplifier to said gate of said output pass element, a gate of said feedback transistor, and a gate of said pole-zero tracking transistor.

8. The low drop-out voltage regulator according to claim 1, wherein said feedback transistor, said pole-zero transistor, and said output pass element are arranged such that for a given gate voltage, the output current from said source of said output pass element is at least 500 times greater than the sum of the output currents from said source of said feedback transistor and said source of the pole-zero tracking transistor.

9. The low drop-out voltage regulator according to claim 4, wherein said switch comprises:

a first current source for providing a bias to said switch, wherein said first current source has an input connected to said unregulated DC input terminal;

a NOT-gate having an input connected to an output of said first current source;

a first transistor having a gate connected to said common gate signal terminal, wherein said first transistor has a source connected to said unregulated DC input terminal;

a first current mirror having a second transistor and a third transistor, wherein said first current mirror is coupled to the output of said first current source and said first transistor; and

a fourth transistor for opening and closing said switch, wherein said fourth transistor has a gate connected to an output of said NOT-gate, said fourth transistor has a source connected to the drain of said pole-zero tracking transistor, and said fourth transistor has a drain connected to said AC feedback terminal.

10. The low drop-out voltage regulator according to claim 4, wherein said switch has a current threshold, wherein said switch opens whenever the current through said switch exceeds said current threshold, and said switch closes whenever the current through said switch decreases below said current threshold.

11. The low drop-out voltage regulator according to claim 2, wherein said large-resistance resistor comprises:

a second current source for providing a bias to said large-resistance resistor, wherein said second current source has an output connected to the ground reference; and

a second current mirror having a fifth transistor and a sixth transistor, wherein said second current mirror is coupled to an input of said second current source, said second current mirror has a source of the fifth transistor and a source of the sixth transistor connected to said DC feedback terminal, and said second current mirror has a drain of said fifth transistor connected to the positive input of said error amplifier.

12. The low dropout voltage regulator according to claim 1, wherein said low voltage drop-out regulator is stable for any parasitic ESR of the output section less than 50 mΩ

.

13. A method of circuit operation in a low drop-out voltage regulator comprising:

accepting a reference voltage at an error amplifier, an output of said error amplifier supplying a common gate signal;

controlling a first transistor by means of the common gate signal to produce an output signal at an output terminal of the voltage regulator from an unregulated input voltage;

controlling a second transistor by means of the common gate signal to supply a high-frequency feedback signal from the unregulated input voltage to an input of said error amplifier;

controlling a third transistor by means of the common gate signal to supply an additional high-frequency feedback signal from the unregulated input voltage via a switch to said input of said error amplifier;

introducing a zero into the transfer function of the voltage regulator by means of a stabilizing-zero resistor, such that the circuit will be stable when the ESR of an output capacitor of the voltage regulator is lower than 50 mΩ

;

varying a frequency of said zero based on a load current value of the output signal generated at said output terminal of the voltage regulator, wherein said switch opens and closes in response to changes in the magnitude of the load current value;

supplying the output signal of the power supply to the input of said error amplifier via a large-resistance resistor, wherein a resistance of said large-resistance resistor is at least 10 MΩ

; and

modulating the common gate signal based on the sum of the high-frequency feedback signals and the output signal supplied to said error amplifier.

14. The method of circuit operation in a low drop-out voltage regulator according to claim 13, wherein said third transistor can be replaced by an array of transistors, wherein each transistor in the array is controlled by the common gate signal, wherein each transistor in the array supplies an additional high-frequency feedback signal from the unregulated input voltage via a switch to the input of the error amplifier, and wherein each switch can have a different output current threshold for opening and closing.

15. The method of circuit operation in a low drop-out voltage regulator according to claim 13, wherein for a given gate voltage, the output current of said first transistor is at least 500 times greater than the sum of the output currents of all other transistors coupled to the unregulated input voltage.