Digital configurable macro architecture

• US 6,765,407 B1
• Filed: 10/15/2002
• Issued: 07/20/2004
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/272,231
• Time in Patent Office: 644 Days
• Field of Search: 326/37-41
• US Class Current: 326/38
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.

Claims

1. A programmable digital device comprising:

a programmable digital circuit block that is configurable to perform any one of a plurality of predetermined digital functions upon being configured with a single register write operation.

2. The programmable digital device as recited in claim 1 wherein said programmable digital circuit block is configurable into a serial arrangement.

3. The programmable digital device as recited in claim 1 wherein said programmable digital circuit block is configurable into a parallel arrangement.

4. The programmable digital device as recited in claim 1 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

5. The programmable digital device as recited in claim 1 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

6. The programmable digital device as recited in claim 1 wherein said predetermined digital functions are 8-bit predetermined digital functions.

7. The programmable digital device as recited in claim 1 wherein said programmable digital circuit block further comprises:

a configuration register for receiving and storing a plurality of configuration data corresponding to any of said plurality of predetermined digital functions; and

a plurality of selectable logic circuits which perform any of said plurality of predetermined digital functions, wherein said predetermined digital functions determine size and arrangement of said selectable logic circuits.

8. A programmable digital device comprising:

an array of programmable digital circuit blocks, each programmable digital circuit block is configurable to perform any one of a plurality of predetermined digital functions upon being configured with a single register write operation.

9. The programmable digital device as recited in claim 8 wherein each programmable digital circuit block is configurable into a serial arrangement.

10. The programmable digital device as recited in claim 8 wherein each programmable digital circuit block is configurable into a parallel arrangement.

11. The programmable digital device as recited in claim 8 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

12. The programmable digital device as recited in claim 8 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

13. The programmable digital device as recited in claim 8 wherein said predetermined digital functions are 8-bit predetermined digital functions.

14. The programmable digital device as recited in claim 8 wherein each programmable digital circuit block further comprises:

a configuration register for receiving and storing a plurality of configuration data corresponding to any of said plurality of predetermined digital functions; and

a plurality of selectable logic circuits which perform any of said plurality of predetermined digital functions, wherein said predetermined digital functions determine size and arrangement of said selectable logic circuits.

15. A method of configuring a programmable digital circuit block, comprising:

selecting one a plurality of predetermined digital functions;

performing a single register write operation to provide to said programmable digital circuit block a plurality of configuration data corresponding to said selected one of said predetermined digital functions; and

configuring said programmable digital circuit block using said configuration data.

16. The method as recited in claim 15 wherein said configuring includes configuring said programmable digital circuit block into a serial arrangement.

17. The method as recited in claim 15 wherein said configuring includes configuring said programmable digital circuit block into a parallel arrangement.

18. The method as recited in claim 15 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM) a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

19. The method as recited in claim 15 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

20. The method as recited in claim 15 wherein said predetermined digital functions are 8-bit predetermined digital functions.