Model-based feed-forward linearization of amplifiers

• US 6,765,440 B2
• Filed: 12/18/2002
• Issued: 07/20/2004
• Est. Priority Date: 12/18/2002
• Status: Expired due to Term

• Current Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.)
• Original Assignee: Andrew Corporation (CommScope Holding Company, Inc.)
• Inventors: Chandrasekaran, Rajiv
• Primary Examiner(s): Shingleton, Michael B.
• Application Number:
  US10/322,953
• Publication Number:
  US 20040119534A1
• Time in Patent Office: 580 Days
• Field of Search: 330/149, 330/151
• US Class Current: 330/149
• CPC Class Codes: H03F 1/3229 using a loop for error extraction and another loop for error subtraction
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence

Abstract

The signal generated by a high-power amplifier (HPA) operating in its non-linear region is linearized by an amplifier circuit using feed-forward compensation in which an auxiliary channel relies on a model of the HPA to generate an auxiliary signal that is combined with the HPA output to generate an amplified linearized output signal. The amplifier circuit may be implemented with a pre-distorter in the main amplifier channel to linearize the HPA using both pre-compensation and feed-forward compensation. Using the HPA model in the auxiliary channel enables the auxiliary signal to be generated without directly relying on the HPA output. This enables the amplifier circuit to be implemented without having to delay the high-power HPA output signal prior to being synchronously combined with the auxiliary signal. In preferred embodiments, the auxiliary channel signal is generated using a relatively low-power amplifier operating in its linear region.

Claims

1. An amplifier circuit adapted to generate a linearized amplified output signal from an input signal, the amplifier circuit comprising:

a main channel adapted to receive the input signal and generate an amplified main channel signal using a main amplifier operated in its non-linear region;

an auxiliary channel adapted to apply the input signal to a model of the main amplifier to generate an auxiliary channel signal; and

a summation node adapted to combine the amplified main channel signal and the auxiliary channel signal to generate the linearized amplified output signal, wherein the auxiliary channel further comprises;

an auxiliary summation node adapted to generate an error signal based on a difference between the input signal and the output of the main amplifier model; and

an auxiliary amplifier adapted to amplify the error signal to generate the auxiliary channel signal.

2. The invention of claim 1, wherein the auxiliary amplifier is operated in its linear region.

3. The invention of claim 1, wherein the power level of the auxiliary amplifier is less than the power level of the main amplifier.

4. The invention of claim 1, wherein the amplified main channel signal is not applied directly to the main amplifier model in generating the auxiliary channel signal.

5. The invention of claim 1, wherein the amplifier circuit is implemented without any high-power delay modules.

6. The invention of claim 1, wherein the amplifier circuit is implemented without any delay module between the output of the main amplifier and the summation node.

7. The invention of claim 1, further comprising a feed-back control channel adapted to generate one or more control signals for controlling operations of one or more components in the main and auxiliary channels.

8. The invention of claim 1, wherein the main channel further comprises a pre-distorter adapted to pre-distort the input signal prior to application to the main amplifier.

9. The invention of claim 1, wherein:

the main channel further comprises a main equalizer adapted to equalize the main channel signal prior to application to the main amplifier; and

the auxiliary channel further comprises an auxiliary equalizer adapted to equalize the error signal, wherein the auxiliary amplifier is adapted to amplify the equalized error signal to generate the auxiliary channel signal.

10. The invention of claim 9, wherein the main channel further comprises a pre-distorter adapted to pre-distort the input signal prior to application to the main equalizer.

11. The invention of claim 9, wherein the auxiliary amplifier is operated in its linear region.

12. The invention of claim 9, wherein the power level of the auxiliary amplifier is less than the power level of the main amplifier.

13. The invention of claim 9, wherein the main and auxiliary equalizers compensate for phase, amplitude, and delay differences between the main and auxiliary channels.

14. The invention of claim 9, further comprising a feed-back control channel adapted to generate one or more control signals for controlling operations of one or more of the main equalizer, the main amplifier model, the auxiliary equalizer, and the auxiliary amplifier.

15. The invention of claim 14, wherein the feed-back control channel comprises:

a switch block adapted to select one or more signals for use in generating the control signals; and

a control algorithm block adapted to generate the one or more control signals from the one or more selected signals.

16. The invention of claim 15, wherein the switch block is adapted to receive and select one or more of (1) the signal input to the main amplifier, (2) the amplified main channel signal output from the main amplifier, (3) the signal input to the auxiliary amplifier, (4) the auxiliary channel signal output from the auxiliary amplifier, and (5) the linearized amplified output signal from the summation node.

17. The invention of claim 9, wherein the main equalizer, the main amplifier model, and the auxiliary equalizer are adapted to operate in a digital domain.

18. The invention of claim 17, wherein:

the amplifier circuit further comprises an analog-to-digital converter (ADC) adapted to digitize an analog input signal for processing by the main and auxiliary channels;

the main channel further comprises a main digital-to-analog converter (DAC) adapted to convert the output of the main equalizer to an analog domain prior to application to the main amplifier; and

the auxiliary channel further comprises an auxiliary DAC adapted to convert the output of the auxiliary equalizer to the analog domain prior to application to the auxiliary amplifier.

19. The invention of claim 18, wherein:

the amplifier circuit further comprises an RF/IF (radio frequency to intermediate frequency) converter adapted to convert an analog RF input signal into an analog IF input signal prior to application to the ADC;

the main channel further comprises a main IF/RF converter adapted to convert the output of the main DAC from IF to RF prior to application to the main amplifier; and

the auxiliary channel further comprises an auxiliary IF/RF converter adapted to convert the output of the auxiliary DAC from IF to RF prior to application to the auxiliary amplifier.

20. A method for generating a linearized amplified output signal from an input signal, the method comprising:

generating an amplified main channel signal based on the input signal using a main amplifier operating in its non-linear region;

generating an auxiliary channel signal based on the input signal using a model of the main amplifier; and

combining the amplified main channel signal and the auxiliary channel signal to generate the linearized amplified output signal, wherein generating the auxiliary channel further comprises;

generating an error signal based on a difference between the input signal and the output of the main amplifier model; and

amplifying the error signal using an auxiliary amplifier to generate the auxiliary channel signal.

21. The invention of claim 20, wherein the auxiliary amplifier is operated in its linear region.

22. The invention of claim 20, wherein the power level of the auxiliary amplifier is less than the power level of the main amplifier.

23. The invention of claim 20, wherein the amplified main channel signal is not applied directly to the main amplifier model in generating the auxiliary channel signal.

24. The invention of claim 20, wherein the method is implemented without any high-power delay modules.

25. The invention of claim 20, wherein the method is implemented without any delay module between the output of the main amplifier and a summation node that combines the amplified main channel signal and the auxiliary channel signal.

26. The invention of claim 20, further comprising generating one or more control signals for controlling operations of one or more components in the main and auxiliary channels.

27. The invention of claim 20, wherein generating the amplified main channel signal comprises pre-distorting the input signal prior to application to the main amplifier.

28. The invention of claim 20, wherein:

generating the amplified main channel signal further comprises equalizing the main channel signal prior to application to the main amplifier; and

generating the auxiliary channel signal further comprises equalizing the error signal, wherein the equalized error signal is amplified using the auxiliary amplifier to generate the auxiliary channel signal.

29. The invention of claim 28, wherein generating the amplified main channel signals further comprises pre-distorting the input signal prior to equalizing.

30. The invention of claim 28, wherein the auxiliary amplifier is operated in its linear region.

31. The invention of claim 28, wherein the power level of the auxiliary amplifier is less than the power level of the main amplifier.

32. The invention of claim 28, wherein equalizing the main channel signal and the error signal compensates for phase, amplitude, and delay differences between the main and auxiliary channels.

33. The invention of claim 28, further comprising generating one or more control signals for controlling operations of one or more of a main equalizer, the main amplifier model, an auxiliary equalizer, and the auxiliary amplifier.

34. The invention of claim 33, wherein generating the one or more control signals comprises:

selecting one or more signals for use in generating the control signals; and

generating the one or more control signals from the one or more selected signals.

35. The invention of claim 34, wherein selecting the one or more signals comprises receiving and selecting one or more of (1) the signal input to the main amplifier, (2) the amplified main channel signal output from the main amplifier, (3) the signal input to the auxiliary amplifier, (4) the auxiliary channel signal output from the auxiliary amplifier, and (5) the linearized amplified output signal from a summation node that combines the amplified main channel signal and the auxiliary channel signal.

36. The invention of claim 28, wherein a main equalizer, the main amplifier model, and an auxiliary equalizer are adapted to operate in a digital domain.

37. The invention of claim 36, further comprising:

digitizing, using an ADC, an analog input signal for processing by the main and auxiliary channels;

converting, using a main DAC, the output of the main equalizer to an analog domain prior to application to the main amplifier; and

converting, using an auxiliary DAC, the output of the auxiliary equalizer to the analog domain prior to application to the auxiliary amplifier.

38. The invention of claim 37, further comprising:

converting an analog RF input signal into an analog IF input signal prior to application to the ADC;

converting the output of the main DAC from IF to RF prior to application to the main amplifier; and

converting the output of the auxiliary DAC from IF to RF prior to application to the auxiliary amplifier.

39. An apparatus for generating a linearized amplified output signal from an input signal, the apparatus comprising:

means for generating an amplified main channel signal based on the input signal using a main amplifier operating in its non-linear region;

means for generating an auxiliary channel signal based on the input signal using a model of the main amplifier; and

means for combining the amplified main channel signal and the auxiliary channel signal to generate the linearized amplified output signal, wherein the means for generating the auxiliary channel signal comprises;

means for generating an error signal based on a difference between the input signal and the output of the main amplifier model; and

means for amplifying the error signal to generate the auxiliary channel signal.

40. An amplifier circuit adapted to generate a linearized amplified output signal from an input signal, the amplifier circuit comprising:

a main channel adapted to receive the input signal and generate an amplified main channel signal using a main amplifier operated in its non-linear region;

an auxiliary channel adapted to apply the input signal to a model of the main amplifier to generate an auxiliary channel signal; and

a summation node adapted to combine the amplified main channel signal and the auxiliary channel signal to generate the linearized amplified output signal, wherein the amplified main channel signal is not applied directly to the main amplifier model in generating the auxiliary channel signal.

41. An amplifier circuit adapted to generate a linearized amplified output signal from an input signal, the amplifier circuit comprising:

a main channel adapted to receive the input signal and generate an amplified main channel signal using a main amplifier operated in its non-linear region;

an auxiliary channel adapted to apply the input signal to a model of the main amplifier to generate an auxiliary channel signal;

a summation node adapted to combine the amplified main channel signal and the auxiliary channel signal to generate the linearized amplified output signal; and

a feed-back control channel adapted to generate one or more control signals for controlling operations of one or more components in the main and auxiliary channels.

42. An amplifier circuit adapted to generate a linearized amplified output signal from an input signal, the amplifier circuit comprising:

a main channel adapted to receive the input signal and generate an amplified main channel signal using a main amplifier operated in its non-linear region;

an auxiliary channel adapted to apply the input signal to a model of the main amplifier to generate an auxiliary channel signal, wherein the main amplifier model models distortion of the main amplifier without generating an amplified signal; and

a summation node adapted to combine the amplified main channel signal and the auxiliary channel signal to generate the linearized amplified output signal.

43. An amplifier circuit adapted to generate a linearized amplified output signal from an input signal, the amplifier circuit comprising:

a main channel adapted to receive the input signal and generate an analog amplified main channel signal using an analog main amplifier operated in its non-linear region;

an auxiliary channel adapted to apply the input signal to a digital model of the analog main amplifier to generate an auxiliary channel signal, wherein the digital model models, in a digital domain, distortion of the analog main amplifier; and

a summation node adapted to combine the amplified main channel signal and the auxiliary channel signal to generate the linearized amplified output signal.

44. The invention of claim 43, wherein the digital model models the distortion of the analog main amplifier without generating an amplified analog signal.