Graphics resampling system and method for use thereof
First Claim
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1. A resampling circuit, comprising:
- first resampling circuitry for calculating row output sample values from input sample values of samples along rows of a source image;
a shift register having an input terminal coupled to the resampling circuit to receive the row output sample values and further having a plurality of evenly spaced sample output terminals, the shift register shifting the row output sample values through the shift register as the row output sample values are calculated; and
second resampling circuitry coupled to the input terminal and the output terminals of the shift register to sample the row output sample values shifting therethrough, the second resampling circuit calculating output sample values from the row output sample values sampled from the sample output terminals.
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Abstract
A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row resampling circuit calculates row output values which are provided to a column resampling circuit that calculates output sample values therefrom. The column resampling circuit includes a shift register that receives the row output values and shifts the row output values through the shift register as the row output samples are calculated. The shift register has a plurality of evenly spaced sample output terminals from which the row output values are sampled by an interpolation circuit for calculation of the output sample values.
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Citations
28 Claims
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1. A resampling circuit, comprising:
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first resampling circuitry for calculating row output sample values from input sample values of samples along rows of a source image;
a shift register having an input terminal coupled to the resampling circuit to receive the row output sample values and further having a plurality of evenly spaced sample output terminals, the shift register shifting the row output sample values through the shift register as the row output sample values are calculated; and
second resampling circuitry coupled to the input terminal and the output terminals of the shift register to sample the row output sample values shifting therethrough, the second resampling circuit calculating output sample values from the row output sample values sampled from the sample output terminals. - View Dependent Claims (2, 3, 4, 5)
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6. A resampling circuit, comprising:
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a row resampling circuit for receiving input sample values of samples along a row of a source image and providing row output values at an output terminal; and
a column resampling circuit coupled to the output terminal of the row resampling circuit, the column resampling circuit calculating output sample values from the row output values provided by the row resampling circuit, the column resampling circuit having a shift register receiving the row output values from the row resampling circuit and shifting the row output values through the shift register as the row output values are calculated, the shift register further having a plurality of evenly spaced sample output terminals at which the row output values are sampled for the output sample value calculation. - View Dependent Claims (7, 8, 9)
a plurality of series coupled registers through which the input sample values are shifted from a first register to a last register, each of the registers having input and output terminals and having a same data capacity; and
an interpolation circuit coupled to the input terminal of the first register and further coupled to the output terminals of each register, the interpolation circuit calculating row output values from the input sample values sampled from the input terminal of the first register and the output terminals of each register.
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8. The resampling circuit of claim 7 wherein each of the data capacity of each register is sufficient to store the graphics data for one sample of the source image.
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9. The resampling circuit of claim 7 wherein the plurality of series coupled registers comprises four series coupled registers.
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10. A graphics processing system, comprising:
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a bus interface for coupling to a system bus;
a graphics processor coupled to the bus interface to process graphics data;
address and data busses coupled to the graphics processor to transfer address and graphics data to and from the graphics processor;
display logic coupled to the data bus to drive a display; and
a resampling circuit coupled to the graphics processor and adapted to calculate output sample values from input sample values corresponding to input samples of a source image that are arranged in rows and columns, the resampling circuit comprising;
first resampling circuitry for calculating row output sample values from input sample values of samples along rows of a source image;
a shift register having an input terminal coupled to the resampling circuit to receive the row output sample values and further having a plurality of evenly spaced sample output terminals, the shift register shifting the row output sample values through the shift register as the row output samples are calculated; and
second resampling circuitry coupled to the input terminal and the output terminals of the shift register to sample the row output sample values shifting therethrough, the second resampling circuit calculating output sample values from the row output sample values sampled from the sample output terminals. - View Dependent Claims (11, 12, 13, 14, 15)
a plurality of series coupled registers through which the input sample values are shifted from a first register to a last register, each of the registers having input and output terminals and having a same data capacity; and
an interpolation circuit coupled to the input terminal of the first register and further coupled to the output terminals of each register, the interpolation circuit calculating row output sample values from the input sample values sampled from the input terminal of the first register and the output terminals of each register.
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14. The graphics processing system of claim 10 wherein the second resampling circuitry of the resampling circuit calculates the output sample values by interpolating from a cubic model.
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15. The graphics processing system of claim 10 wherein the second resampling circuitry of the resampling circuit calculates the output samples from a first interpolation model for row output samples representing text images and from a second interpolation model for row output samples representing video images.
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16. A computer system, comprising:
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a system processor;
a system bus coupled to the system processor;
a system memory coupled to the system bus; and
a graphics processing system coupled to the system bus, the graphics processing system, comprising;
a bus interface for coupling to a system bus;
a graphics processor coupled to the bus interface to process graphics data;
address and data busses coupled to the graphics processor to transfer address and graphics data to and from the graphics processor;
display logic coupled to the data bus to drive a display; and
a resampling circuit coupled to the graphics processor and adapted to calculate output sample values from input sample values corresponding to input samples of a source image that are arranged in rows and columns, the resampling circuit comprising;
first resampling circuitry for calculating row output sample values from input sample values of samples along rows of a source image;
a shift register having an input terminal coupled to the resampling circuit to receive the row output sample values and further having a plurality of evenly spaced sample output terminals, the shift register shifting the row output sample values through the shift register as the row output samples are calculated; and
second resampling circuitry coupled to the input terminal and the output terminals of the shift register to sample the row output sample values shifting therethrough, the second resampling circuit calculating output sample values from the row output sample values sampled from the sample output terminals. - View Dependent Claims (17, 18, 19, 20)
a plurality of series coupled registers through which the input sample values are shifted from a first register to a last register, each of the registers having input and output terminals and having a same data capacity; and
an interpolation circuit coupled to the input terminal of the first register and further coupled to the output terminals of each register, the interpolation circuit calculating row output sample values from the input sample values sampled from the input terminal of the first register and the output terminals of each register.
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19. The computer system of claim 16 wherein the second resampling circuitry of the resampling circuit calculates the output sample values by interpolating from a cubic model.
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20. The computer system of claim 16 wherein the second resampling circuitry of the resampling circuit calculates the output samples from a first interpolation model for row output samples representing text images and from a second interpolation model for row output samples representing video images.
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21. A method for calculating output sample values from input sample values corresponding to input samples of a source image that are arranged in rows and columns, respectively, the method comprising:
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calculating row output values from a span of input samples for a plurality of adjacent rows;
providing the calculated row output values for the span of input samples for the plurality of adjacent rows to a first register of a plurality of series coupled registers;
sampling a plurality of row output values spaced at equal intervals in response to the calculation of a row output value; and
calculating output values from the sampled row output values. - View Dependent Claims (22, 23, 24)
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25. A method for calculating output sample values from input sample values of corresponding samples that arranged in rows and columns, the method comprising:
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calculating row sample values from the input sample values of a portion of samples from a plurality of adjacent rows;
selecting a portion of row samples from a plurality of adjacent rows;
sampling a row sample value from each of the portions of row samples of adjacent rows, the sampled row sample value of each portion located in the same relative position within the respective portion of row samples; and
calculating output values from the sampled row sample values. - View Dependent Claims (26, 27, 28)
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Specification