Integrated systems using vertically-stacked three-dimensional memory cells

• US 6,765,813 B2
• Filed: 06/27/2002
• Issued: 07/20/2004
• Est. Priority Date: 08/14/2000
• Status: Expired due to Term

• Current Assignee: Innovative Memory Systems, Inc. (Wi-LAN Inc.)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Lysaght, Colm P., Scheuerlein, Roy E., Moore, Christopher S., Ilkbahar, Alper, Tringali, J. James, Friedman, David R.
• Primary Examiner(s): Lam, David
• Application Number:
  US10/185,588
• Publication Number:
  US 20020163834A1
• Time in Patent Office: 754 Days
• Field of Search: 365/51, 365/52, 365/63, 365/130, 365/185.04, 365/104, 365/94, 361/735, 361/803
• US Class Current: 365/51
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

Support circuitry for a three-dimensional memory array is formed in a substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Claims

1. An integrated circuit comprising:

a substrate;

a three-dimensional memory array comprising a plurality of layers of memory cells stacked vertically above one another and above the substrate;

support circuitry for the three-dimensional memory array, the support circuitry formed in the substrate at least partially under the three-dimensional memory array, the support circuitry defining open area in the substrate under the three-dimensional memory array; and

a second memory array formed at least partially in the open area in the substrate under the three-dimensional memory array.

2. The invention of claim 1 further comprising wire connections to the second memory array passing through the support circuitry for the three-dimensional memory array.

3. The invention of claim 1, wherein the second memory array is partitioned into multiple parts and more than one part is accessed in parallel.

4. The invention of claim 1, wherein the three-dimensional memory array and the second memory array are partitioned into banks, and wherein one or more banks are accessed in parallel.

5. The invention of claim 1, wherein the three-dimensional memory array is organized in a plurality of sub-arrays, and wherein the second memory array is formed at least partially in the substrate between the support circuitry for at least one of the sub-arrays.

6. The invention of claim 1, wherein the three-dimensional memory array is organized in a plurality of sub-arrays of first and second types, the first type being above bit line support circuitry and the second type being above word line support circuitry, wherein the second memory array is formed at least partially in the substrate under at least one of the first and second types of sub-arrays.

7. The invention of claim 1, wherein the second memory array is completely surrounded by the support circuitry.

8. The invention of claim 1, wherein the second memory array is partially surrounded by the support circuitry.

9. The invention of claim 1, wherein the support circuitry comprises a multi-headed driver decode circuit.

10. The invention of claim 1 further comprising a third memory array formed at least partially in the open area in the substrate under the three-dimensional memory array.

11. The invention of claim 1 further comprising logic circuitry formed at least partially in the open area in the substrate under the three-dimensional memory array.

12. The invention of claim 1, wherein the second memory array comprises a cache memory.

13. The invention of claim 1, wherein the three-dimensional memory array comprises non-volatile memory cells, and wherein the second memory array comprises volatile memory cells.

14. The invention of claim 1, wherein both the three-dimensional memory array and the second memory array comprise non-volatile memory cells.

15. The invention of claim 1, wherein the three-dimensional memory array stores data, and wherein the second memory array stores code.

16. The invention of claim 1, wherein the three-dimensional memory array is configured as NAND memory, and wherein the second memory array is configured as NOR memory.

17. The invention of claim 1, wherein at least some memory cells of the second memory array are pitch-matched to at least some memory cells of the three-dimensional memory array.

18. The invention of claim 1, wherein the integrated circuit is part of a modular memory device that is removably connectable to a host device.

19. The invention of claim 1, wherein the memory cells of one of the three-dimensional memory array and the second memory array comprises field-programmable write-once memory cells, and wherein the other of the three-dimensional memory array and the second memory array comprises field-programmable re-writable memory cells.

20. The invention of claim 1, wherein the memory cells of the three-dimensional memory array and the second memory array have different write times.

21. The invention of claim 1, wherein the memory cells of the three-dimensional memory array and the second memory array have different read times.

22. The invention of claim 1, wherein the memory cells of one of the three-dimensional memory array and the second memory array are programmed during manufacturing, and wherein the other of the three-dimensional memory array and the second memory array are programmed in the field.

23. The invention of claim 22, wherein the memory cells programmed during manufacturing store register settings, and wherein the memory cells programmed in the field store data.

24. The invention of claim 1, wherein the memory cells of the three-dimensional memory array store a different data type than the memory cells of the second memory array.

25. The invention of claim 24, wherein the memory cells of the three-dimensional memory array store a file system structure, and wherein the memory cells of the second memory array store a digital media file.

26. The invention of claim 24, wherein the memory cells of the three-dimensional memory array are assigned a different level of cache hierarchy than the memory cells of the second memory array.

27. An integrated circuit comprising:

a substrate;

a three-dimensional memory array comprising a plurality of layers of memory cells stacked vertically above one another and above the substrate;

support circuitry for the three-dimensional memory array, the support circuitry formed in the substrate at least partially under the three-dimensional memory array, the

support circuitry defining open area in the substrate under the three-dimensional memory array; and

logic circuitry formed at least partially in the open area in the substrate under the three-dimensional memory array.

28. The invention of claim 27, wherein wire connections to the logic circuitry pass through the support circuitry for the three-dimensional memory array.

29. The invention of claim 27 further comprising a second memory array formed at least partially in the open area in the substrate under the three-dimensional memory array.

30. The invention of claim 27, wherein the logic circuitry comprises host device interface circuitry.

31. The invention of claim 30, wherein the logic circuitry comprises second host device interface circuitry.

32. The invention of claim 27, wherein the logic circuitry comprises an ISA interface operative to allow the three-dimensional memory array to behave as a disk drive.

33. The invention of claim 27, wherein the logic circuitry comprises an audio decoder.

34. The invention of claim 27, wherein the logic circuitry comprises a microprocessor.

35. The invention of claim 27, wherein the integrated circuit is part of a modular memory device that is removably connectable to a host device.