Communication method of contactless ID card and integrated circuit used in communication method

• US 6,765,959 B1
• Filed: 06/04/1999
• Issued: 07/20/2004
• Est. Priority Date: 06/05/1998
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Tanaka, Satoshi, Ishifuji, Tomoaki, Nagai, Kenji, Furukawa, Katsuhiro
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/325,801
• Time in Patent Office: 1,873 Days
• Field of Search: 375/238, 375/239, 375/226, 375/293, 375/287, 375/316, 375/295, 375/340, 375/360, 375/371, 375/350, 348/164, 327/26, 327/36-50, 327/85, 327/141, 327/144, 327/164, 327/165, 329/327, 329/341, 329/343
• US Class Current: 375/239
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

The code system is realized by that a plurality of waveforms A and B each having duty ratios of 50% in which only any one of a rising edge and a falling edge is present are combined with each other, and “1” and “0” are allocated to the combined waveform. In accordance with the present invention, both a clock and data can be transmitted at the same time, and can be readily demodulated without using a complex PLL circuit. As a trial manufacture according to the present invention, the demodulator could be realized which could allow variations contained in an input frequency by more than 1 digit under operating voltage of 2 V. The effectiveness of this patent could be confirmed.

Claims

1. A communication method using a first waveform and a second waveform, wherein said first waveform representing one level of data signal and said second waveform representing another level of data signal are formed by combining a plurality of waveform patterns having at center portions thereof, a transition of any one of a rising edge and a falling edge;

and for data communication carried out by employing said first waveform and said second waveform, said data communication is performed in such a manner that said one transition does not occur except for at center portions of the waveform patterns; and

said transitions to be detected at the center portions of any combinations of said first waveform and said second waveform are the same ones as said rising edge and said falling edge.

2. A communication method with employment of a code for representing a logic state by way of plural sorts of waveforms having transitions in equi-intervals, which are commonly used for any one of a rising edge and a falling edge, wherein:

in such a case that each of a first waveform and a second waveform is filtered by a low-pass filer, and a filter output is monitored at a timing of a commonly existing transition, a communication code capable of selecting logic levels different with respect to two waveforms is employed;

wherein;

with respect to the plural sorts of first waveforms and second waveforms, which have the transitions commonly applied to any one of the rising edge and the falling edge, the following communication code is employed in which the stage number of the transitions of the second waveform is larger than that of the first waveform;

an initial state of the first waveform is equal to a first stage;

a final state of the first waveform is equal to a second state;

initial states of a plurality of said second waveforms are equal to initial states;

final states of the second plural waveforms are equal to first states;

the first waveforms which are continued more than two times are allocated to a first logic value; and

combined waveforms produced by combining the first waveform with the second waveform which is not continued is allocated to a second logic value.

3. A communication method as claimed in claim 2, wherein:

a communication code is employed in which a waveform is made in correspondence to either the first waveform or the second waveform, in which a high level state thereof is extended by T/2 (symbol “

T”

being 1 time period) along a positive time direction and a low level state thereof is extended by T/2 along a negative time direction from each of the rising edge timing;

such a waveform is allocated to either the first waveform or the second waveform, in which a high level state thereof is held by time “

t1”

along a positive time direction from the rising edge time, time “

t2”

up to a remaining center point is held under low level state;

a low level state thereof is held by time “

t1”

along a negative time direction from the rising edge time, and time “

t2”

up to a remaining center point is held under high level state; and

also such a condition of (t1+t2=T/2) is applied.

4. A communication method as claimed in claim 3 wherein a communication code is employed, in which a rising edge is replaced by a falling edge, and a high level state is replaced by a low level state.

5. A communication method as claimed in claim 3 wherein:

a communication code is employed, in which a waveform is allocated to either the second waveform or the first waveform, such that a high level state thereof is maintained by time “

t11”

along a positive time direction from rising edge time, a low level state thereof is held by time “

t21”

along a negative time direction from the rising edge time, and time “

t22”

up to a remaining center point is held under high level state; and

also such a condition of (t11+t22=T/2) is applied, and also, another condition of (t12+t21=T/2) is applied.

6. A communication method as claimed in claim 5 wherein a communication code is employed, in which a rising edge is replaced by a falling edge, and a high level state is replaced by a low level state.

7. An integrated circuit comprising:

a buffer circuit having an input terminal to receive an input data signal of said integrated circuit, a first output terminal, and a second output terminal to output the same signal as that of said first output terminal thereof;

a low-pass filter circuit having an input terminal and an output terminal, said first output terminal of said buffer circuit being connected to said input terminal of said low-pass filter circuit;

a latch circuit having a first input terminal, a second input terminal, and an output terminal, said output terminal of said low-pass filter circuit being connected to said first input terminal of said latch circuit; and

a pulse generating circuit having an input terminal and an output terminal to provide said latch circuit with an edge trigger to drive said latch circuit, said second output terminal of said buffer circuit being connected to said input terminal of said pulse generating circuit, and said output terminal of said pulse generating circuit being connected to said second input of said latch circuit,

wherein said latch circuit is configured so that an output of said pulse generating circuit may be inputted thereto through said second terminal thereof performing as a clock input terminal, to be driven at one of a rising edge and a falling edge of an original waveform of said input data signal.

8. An integrated circuit as claimed in claim 7 wherein:

the low-pass filter circuit is constituted by a first resistor and a first capacitor;

a first terminal of the first resistor is used as a first terminal;

a second terminal of said resistor is connected to a first terminal of the first capacitor;

a second terminal of said first capacitor is connected to the ground potential; and

the first terminal of said first capacitor is used as an output terminal of the low-pass filter circuit.

9. An integrated circuit as claimed in claim 7 wherein:

the low-pass filter circuit is constituted by a first resistor and a second capacitor;

a first terminal of the first resistor is used as a first terminal;

a second terminal of said resistor is connected to a first terminal of a first capacitor;

a second terminal of said first capacitor is connected to the ground potential;

the first terminal of said second capacitor is connected to the second terminal of the first resistor;

a second terminal of said second capacitor is connected to a power supply potential; and

the first terminal of said second capacitor is used as an output terminal of the low-pass filter circuit.

10. An integrated circuit according to claim 7, further comprising of:

a 1-bit counter set in the case that an output state of a first latch circuit is brought into a high level state;

a register set in the case that the output state of the first latch circuit is brought into the high level state;

a second latch circuit driven in a phase opposite to that of the first latch circuit, and for entering thereinto an output signal of the first latch circuit as an input; and

a master/slave flip-flop for entering thereinto an output signal of the second latch circuit as an input; and

wherein;

an AND-gated value obtained from outputs of the counter and register is used as a clock signal of the master/slave flip-flop.

11. An integrated circuit wherein:

in addition to the integrated an electronic circuit constituted by a first buffer circuit, a first low-pass filter, a first latch circuit, and a first positive, or negative edge trigger circuit, an integrated circuit wherein;

a first output terminal of a buffer circuit which receives an input data signal is connected to an input of a low-pass filter circuit;

an output terminal of the low-pass filter circuit is connected to an input terminal of a latch circuit;

either the first output terminal of the buffer circuit or a second terminal for outputting the same signal as that of the first output terminal is connected to an input terminal of a pulse generating circuit; and

an output of the pulse generating circuit is entered into a clock input terminal of a latch;

first to third master/slave flip-flops, a second latch circuit, first and second OR gate circuits, a first AND gate circuit, and first and second inverter circuits;

the output terminal of the first latch circuit is connected to a first input terminal of the first AND gate circuit;

an output of the first OR gate circuit is connected to an input of the first master/slave flip-flop;

an output of the first master/slave flip/flop is connected to an input of the first inverter circuit;

an output of the first inverter circuit is connected to a second input terminal of the first OR gate circuit;

an output terminal of the first latch circuit is connected to the first input terminal of the second OR gate circuit;

an output of said second OR gate circuit is connected to an input of the second master/slave flip-flop;

an output of said second master/slave flip-flop is connected to the second input terminal of said second OR gate circuit;

an output of said first latch circuit is connected to an input terminal of said second latch circuit;

an output of said second latch circuit is connected to an input terminal of said third master/ slave flip-flop circuit;

an output terminal of the third master/slave flip-flop circuit is used as a data output terminal;

an output terminal of the first master/slave flip-flop circuit is connected to a first input of the first AND gate circuit;

an output terminal of the second master/slave flip-flop circuit is connected to a second input of the first AND gate circuit;

a first output terminal of the first AND gate circuit is connected to a clock input terminal of the third master/slave flip-flop circuit;

the first output terminal of the first AND gate circuit is connected to the second inverter circuit;

a signal having a phase opposite to that of the output signal from the first output terminal of the first buffer circuit is inputted to both master portions of said first and second master/slave flip-flops and also a clock input terminal of the second latch circuit; and

further,

a signal having the same phase as that of the output signal from the first output terminal of said first buffer circuit is entered into slave portions of said first and second master/slave flip-flops.

12. A transmitter for producing a first waveform and a second waveform to thereby transmit the first waveform and the second waveform, wherein:

said first waveform representing one level of data signal and said second waveform representing another level of data signal are formed by combining a plurality of waveform patterns having at center portions thereof, a transition of any one of a rising edge and a falling edge; and

when both said first waveform and said second waveform are transmitted, said one transition does not occur except for at the center portions of the waveform patterns; and

said transitions to be detected at the center portions of any combinations of said first waveform and said second waveform are the same ones as said rising edge and said falling edge.

13. A receiver for receiving a first waveform and a second waveform, wherein:

said first waveform representing one level of data signal and said second waveform representing another level of data signal are formed by a plurality of waveform patterns having at center portions thereof, a transition of any one of a rising edge and a falling edge;

when both said first waveform and said second waveform are transmitted, said one transition does not occur except for at center portions of the waveform patterns; and

said transitions to be detected at the center portions of any combinations of said first waveform and said second waveform are the same ones as said rising edge and said falling edge.