PCM codec and modem for 56k bi-directional transmission

• US 6,765,967 B2
• Filed: 02/14/2003
• Issued: 07/20/2004
• Est. Priority Date: 01/14/1999
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Eric M. Dowling
• Inventors: Dowling, Eric Morgan
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Kim, Kevin
• Application Number:
  US10/365,829
• Publication Number:
  US 20030156632A1
• Time in Patent Office: 522 Days
• Field of Search: 375/222, 375/254, 379/442, 379/22, 379/399.01, 379/406.08, 370/352, 370/292, 370/276, 370/286
• US Class Current: 375/254
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex

Abstract

A high-speed analog subscriber modem operates at speeds as high as 64 kbps in both the downlink and uplink directions using a standard POTS line augmented with an enhanced codec. This enables increased upload speeds and supports 56 kbps peer-to-peer analog subscriber connections. An enhanced network codec according to the present invention supports on a POTS line both high-speed modem communications and standard PCM speech communication. The enhanced codec of the present invention may be designed to be plug-compatible with existing codecs and may be used to upgrade POTS service to support data rates approaching 64 kbps. Similarly, the present invention may be used to increase the use of the POTS channel in a DSL system.

Claims

1. For use in a network line card, an enhanced codec apparatus, comprising:

a digital signal processor circuit;

a digital interface port with a first coupling to said digital signal processor circuit and a second coupling to a digital network interface port of a digital telecommunication network;

a digital conversion subsystem comprising a DAC wherein said DAC has a digital input coupled to receive a digitally encoded signal sample derived from said digital interface port and an analog output coupled to a first analog signal port, said digital conversion subsystem also comprising an ADC that has a digital output and an analog input;

an echo canceller processing module comprising an adaptive filter and a summing module, said echo canceller processing module controllably coupled to said digital signal processing circuit and operatively coupled to receive at an X-input to said adaptive filter a digital representation of a signal derived from said digital interface port, said echo canceller processing module also operatively coupled to receive at a first input to said summing module, a signal that passes through a second analog signal port, said echo canceller processing module also operatively coupled to receive at a second input to said summing module, an output signal from said adaptive filter, said echo canceller processing module operative to cancel an echo component which leaks from the output of said first analog signal port back into the input of said second analog signal port when said first and second analog signal ports are coupled to a subscriber line;

a pulse decoder processing module controllably coupled to said digital signal processing circuit and having an input operatively coupled to the output of said summing module, said pulse decoder processing module operative to regenerate a PCM data stream; and

a protocol detect processing module controllably coupled to said digital signal processing circuit, said protcol detect processing module operative to detect a transmission protocol used within said POTS portion of said subscriber line and select a pulse decoder mapping operation in response thereto;

wherein said enhanced codec apparatus is adapted to receive at the analog input to the ADC a signal comprising a high speed pulse upstream modem data signal, thereby enabling a substantially symmetric pair of high-speed pulse modem communication channels in the upstream and downstream directions.

2. The enhanced codec apparatus according to claim 1, wherein high-speed communications involves a data rate in the range from 33.6 kbps to 56 kbps.

3. The enhanced codec apparatus according to claim 1, further comprising a chip carrier package which is pin-compatible with an existing PCM codec, whereby an existing line card can be upgraded to an enhanced line card by replacing said existing codec with said enhanced codec.

4. The enhanced codec apparatus according to claim 1, further comprising an out-of-band DSL processing circuit for processing DSL modem signals.

5. The enhanced codec according to claim 1, wherein said ADC samples its input at a first sample rate higher than a second sample rate employed by said digital interface.

6. The enhanced codec apparatus according to claim 1, wherein said protocol detect module is further operative to detect an echo canceller training phase in said protocol and said enhanced codec further comprises:

an echo canceller training module controllably coupled to said digital signal processing circuit and operatively coupled to receive the detection output of said protocol detect module, said echo canceller training module operative train said echo canceller when an echo canceller training phase is detected by said protocol detect processing module.

7. The enhanced codec apparatus according to claim 1, wherein said protocol detect module is further operative to detect a subscriber line equalizer training phase in said protocol and said enhanced codec further comprises:

an equalizer processing module controllably coupled to said digital signal processing circuit and operatively coupled to receive the detection output of said protocol detect module and having an output operatively coupled to the input of said pulse decoder.

8. The enhanced codec apparatus according to claim 7, wherein said ADC samples its input at a first sample rate higher than a second sample rate employed by said digital interface, and said equalizer and pulse decoder processing modules process information at said first sample rate to produce a re-encoded output at said second sample rate.

9. The enhanced codec apparatus according to claim 1, further comprising:

a programmable instruction memory;

wherein said protocol detect module detects a management protocol sequence and responds thereto by loading a new program instruction into said instruction memory.

10. The enhanced codec apparatus according to claim 1, further comprising:

a first filter interposed between the analog output of said DAC and said first analog signal port; and

a second filter interposed between said second analog signal port and the analog input of said ADC.

11. The enhanced codec apparatus according to claim 1, further comprising the network line card.

12. The enhanced codec apparatus according to claim 11, further comprising a network interface equipment rack into which are plugged at least one of said line cards.

13. The method of claim 1, wherein the high speed pulse upstream modem data signal uses a pulse set that is substantially the same as one defined by the V.90 high-speed pulse downlink protocol.

14. For use in a network line card, an enhanced codec apparatus comprising:

a digital to analog converter;

an analog-to-digital converter;

a mapping function module;

a protocol detect module;

a protocol handshake module;

an echo canceller with an X-input coupled to the input of the digital-to-analog converter and a D-input coupled to the output of the analog-to-digital converter, said echo canceller operative to cancel an echo component leaking from the output of said digital-to-analog converter back to the input of the analog-to-digital converter;

wherein said protocol detect module is operative to detect when a signal received at said analog-to-digital converter comprises a data signal, and when a data signal is detected, to further detect a protocol being employed by the data signal, and in response to a detection of a high speed pulse uplink protocol, to activate the protocol handshake module which then causes a high-speed pulse upstream data communication channel and a high-speed pulse downstream data communication channel to be negotiated for subsequent substantially symmetric communication at a speed within the range from 33.6 kps to 64 kbps.

15. The apparatus of claim 14, wherein when the protocol detection module does not detect a protocol, the enhanced codec behaves like a non-enhanced codec by performing upstream and downstream data conversions without applying pulse modem processing.

16. The apparatus of claim 14, wherein said mapping function module further comprises a digital impairment compensation module.

17. The apparatus of claim 14, wherein the high-speed pulse uplink protocol uses a pulse set that is substantially the same as one defined by the V.90 high-speed pulse downlink protocol.

18. A subscriber modem apparatus coupleable to the POTS channel of a subscriber line and operative to communicate with an enhanced codec, the apparatus comprising:

an enhanced protocol module, said enhanced protocol module operative to perform protocol handshaking with a far end communication device via a POTS channel, and if said far end communication device is found to comprise said enhanced codec, to perform protocol handshaking to cause an upstream echo canceller to be trained in said enhanced codec, and to negotiate an upstream pulse signal constellation for high-speed pulse upstream transmission; and

a high-speed pulse uplink transmitter adapted to transmit a high-speed pulse modem signal onto the POTS channel of said subscriber line for reception by said enhanced codec;

whereby said enhanced codec can convert said high-speed pulse modem signal into a PCM data stream and the combination of the enhanced codec and the subscriber modem apparatus can provide substantially symmetric high-speed data communication rates in an uplink and a downlink direction using the negotiated high-speed pulse communication protocol.

19. The subscriber modem apparatus of claim 18, wherein the high-speed pulse modem'"'"'s signal constellation uses a pulse set that is substantially the same as one defined by the V.90 high-speed pulse downlink protocol.

20. A method of processing for use in an enhanced codec, the method comprising the steps of:

monitoring signal traffic occurring at a network interface between a digital network and the POTS channel of a subscriber line;

detecting a signal protocol indicative of the use of a high-speed pulse uplink protocol on said POTS channel;

when said step of detecting indicates said high-speed pulse uplink protocol, enabling an echo canceller and a pulse decoder to receive from said POTS channel an uplink signal that is governed by said high-speed pulse uplink protocol; and

when said step of detecting indicates the absence of said high-speed pulse uplink protocol, disabling at least said pulse decoder to allow a baseband signal to be passed through the enhanced codec without processing via the high-speed pulse uplink protocol.

21. The method of claim 20, wherein the high-speed pulse uplink protocol uses a pulse set that is substantially the same as one defined by the V.90 high-speed pulse downlink protocol.