Power sequencer control circuit

• US 6,766,222 B1
• Filed: 06/14/2000
• Issued: 07/20/2004
• Est. Priority Date: 06/14/2000
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Duley, Raymond S.
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): KOSOWSKI, ALEXANDER J
• Application Number:
  US09/594,220
• Time in Patent Office: 1,497 Days
• Field of Search: 700/297, 700/292, 700/286, 700/295, 700/296, 700/298, 323/238, 307/139, 307/141.8, 307/41, 307/141, 713/330, 361/196, 361/195, 361/197-202, 361/189-191
• US Class Current: 700/286
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips

Abstract

A system and method are presented for sequentially applying electrical power to multiple loads. The system is capable of operating in conjunction with other such systems as either a slave or master. When operating as a master, the system is activated as soon as it is turned on, and begins sequentially applying power to the loads connected to its output channels. When operating as a slave, the system must first receive an enable input signal from the master to which it is connected. The master/slave assignment is switch-selectable; thus, series-connected units may be reconfigured from single to multiple masters, or vice-versa, with no wiring changes. The new system is believed to provide the benefits of improved reliability and reduced cost for power distribution networks, by eliminating startup current surges resulting from simultaneously powering-up all of the attached loads, thereby reducing stress on components.

Claims

1. A method for connecting a plurality of loads to an electrical power source, said method comprising:

consecutively connecting, through a first connection circuit, each of a first plurality of loads to the power source at prescribed time intervals determined by successive transitions of a clock signal, wherein said first connection circuit is configured such that it connects none of the first plurality of loads to the power source until it receives an enable input signal from a third connection circuit; and

coincident with connecting a last one of the plurality of loads to the power source, forwarding an enable output signal to a second connection circuit for connecting a second plurality of loads to the power source.

2. The method as recited in claim 1, wherein connecting the first plurality of loads to the power source is delayed for a prescribed interval following activation of the power source.

3. The method as recited in claim 1, wherein the electrical power source is 220 VAC or 110 VAC line voltage.

4. The method as recited in claim 1, wherein the electrical power source is a DC voltage of at least 12 Volts.

5. The method as recited in claim 1, wherein the prescribed time intervals are at least 0.016 seconds.

6. The method as recited in claim 1, wherein the loads comprise devices or systems capable of being operated from the electrical power source.

7. A system for connecting a plurality of loads to an electrical power source, comprising:

a timing signal source;

a distribution network, adapted to receive the timing signal, and distribute multiple progressively-delayed signals determined by successive transitions of the timing signal;

a plurality of controllable power switching elements, each of which may be activated by one of the multiple progressively-delayed signals; and

control circuitry, adapted to generate an enable output signal when all of the controllable power switching elements are active, wherein the control circuitry is adapted to inhibit operation of the distribution network until it receives an enable input signal so that none of the loads are connected to the electrical power source until after the enable input signal has been received.

8. The system as recited in claim 7, wherein the control circuitry is adapted to inhibit operation of the distribution network for a prescribed interval following initial activation of the power source so that none of the loads are connected to the power source until after the prescribed interval following initial activation of the power source.

9. The system as recited in claim 7, wherein the distribution network comprises a shift register having a serial input and parallel outputs.

10. The system as recited in claim 7, wherein the controllable power switching elements comprise electromechanical or solid-state relays.

11. The system as recited in claim 7, wherein the timing source, control circuitry and distribution network are combined on an integrated circuit.

12. The system as recited in claim 7, wherein the distribution network includes current-amplifying devices capable of activating the power switching elements.

13. The system as recited in claim 7, wherein the timing source, control circuitry and distribution network are implemented as an execution device.

14. The system as recited in claim 13, wherein the execution device comprises a microcontroller.

15. A connection circuit, comprising:

a first input terminal coupled to receive a first power supply voltage;

a second input terminal coupled to receive an enable input signal;

a first output terminal coupled to transmit an enable output signal; and

a second set of output terminals adapted to couple the first power supply voltage to a plurality of load circuits at intervals determined by successive transitions of a clock signal, separate and distinct from another plurality of load circuits adapted also for connection to a second power supply voltage;

wherein the connection circuit is configured such that it connects none of the first plurality of loads to the power source until it receives an enable input signal from a third connection circuit.

16. The connection circuit as recited in claim 15, further comprising shift registers and drivers serving as a distribution network for transmitting progressively delayed versions of a timing signal.

17. The connection circuit as recited in claim 15, further comprising a plurality of power switching elements sequentially activated by progressively delayed timing signals.

18. The connection circuit as recited in claim 15, wherein the connection circuit may be configured as a first group of master and slave units coupled in series with a second group of master and slave units, whereby a master within the second group can be configured to ignore an enable input signal sent from a master within the first group.

19. A method for connecting a plurality of loads to an electrical power source, said method comprising:

consecutively connecting, through a first connection circuit, each of a first plurality of loads to the power source in response to a respective one of a plurality of successive transitions of a clock signal; and

coincident with connecting a last one of the plurality of loads to the power source, forwarding an enable output signal to a second connection circuit for connecting a second plurality of loads to the power source;

wherein said first connection circuit comprises a shift register including a plurality of bit positions and wherein each bit position corresponds to a respective power connection of one of said plurality of loads; and

wherein said shift register is configured to propagate an enable signal from a given bit position to an adjacent bit position in response to a given successive transition of said clock signal, and wherein said first connection circuit is further configured to connect the respective power connection corresponding to said adjacent bit position to the power source in response to said propagating.

20. The method as recited in claim 19, wherein connecting the first plurality of loads to the power source is delayed for a prescribed interval following activation of the power source.

21. The method as recited in claim 19, wherein said first connection circuit may be configured such that it connects none of the first plurality of loads to the power source until it receives an enable input signal from a third connection circuit.

22. The method as recited in claim 19, wherein the electrical power source is 220 VAC or 110 VAC line voltage or a DC voltage of at least 12 Volts.

23. The method as recited in claim 19, wherein the loads comprise devices or systems capable of being operated from the electrical power source.

24. A system for connecting a plurality of loads to an electrical power source, comprising:

a timing signal source;

a distribution network, adapted to receive the timing signal, and distribute multiple progressively-delayed signals, wherein each progressively-delayed signal is asserted in response to a respective one of a plurality of successive transitions of the timing signal;

a plurality of controllable power switching elements, each of which may be activated by an assertion of a corresponding one of the multiple progressively-delayed signals;

a shift register including a plurality of bit positions, wherein each bit position corresponds to a respective one of said multiple progressively-delayed signals, wherein-said shift register is configured to propagate an enable signal from a given bit position to an adjacent bit position in response to a given successive transition of said timing signal, and wherein said distribution network is further configured to assert the progressively-delayed signal corresponding to said adjacent bit position in response to said propagating; and

control circuitry, adapted to generate an enable output signal when all of the controllable power switching elements are active.

25. The system as recited in claim 24, wherein said control circuitry is configurable as either master or slave, and wherein if the control circuitry is configured as a slave the control circuitry is adapted to inhibit operation of the distribution network until it receives an enable input signal so that none of the loads are connected to the electrical power source until after the enable input signal has been received.

26. The system as recited in claim 24, wherein the control circuitry is adapted to inhibit operation of the distribution network for a prescribed interval following initial activation of the power source so that none of the loads are connected to the power source until after the prescribed interval following initial activation of the power source.

27. The system as recited in claim 24, wherein the controllable power switching elements comprise electromechanical or solid-state relays.

28. The system as recited in claim 24, wherein the timing source, control circuitry and distribution network are combined on an integrated circuit.

29. The system as recited in claim 24, wherein the distribution network includes current-amplifying devices capable of activating the power switching elements.

30. A connection circuit, comprising:

a first input terminal coupled to receive a first power supply voltage;

a second input terminal coupled to receive an enable input signal;

a first output terminal coupled to transmit an enable output signal; and

a second set of output terminals adapted to couple the first power supply voltage to each of a plurality of load circuits in response to a respective one of a plurality of successive transitions of a clock signal, separate and distinct from another plurality of load circuits adapted also for connection to a second power supply voltage;

wherein the connection circuit is configured such that it connects none of the first plurality of loads to the power source until it receives an enable input signal from a third connection circuit.

31. The connection circuit as recited in claim 30, further comprising shift registers and drivers serving as a distribution network for transmitting progressively delayed versions of a timing signal.

32. The connection circuit as recited in claim 30, further comprising a plurality of power switching elements sequentially activated by progressively delayed timing signals.

33. The connection circuit as recited in claim 30, wherein the connection circuit may be configured as a first group of master and slave units coupled in series with a second group of master and slave units, whereby a master within the second group can be configured to ignore an enable input signal sent from a master within the first group.