Calibration method implementing segmented flash memory and RAM overlay

• US 6,766,425 B2
• Filed: 05/16/2002
• Issued: 07/20/2004
• Est. Priority Date: 05/16/2002
• Status: Expired due to Fees

• Current Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Original Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Inventors: Burkholder, Larry D., Hedges, Mary T., Allen, W. James, Fildes, Roy M., Mc Cormick, Ben F II, Deutscher, Dale W., Gertiser, Kevin M., Grimm, Charles M.
• Primary Examiner(s): MOAZZAMI, NASSER G
• Application Number:
  US10/146,776
• Publication Number:
  US 20030217222A1
• Time in Patent Office: 796 Days
• Field of Search: 711/103, 711/152-153, 711/163, 711/170, 711/173, 701/1, 701/35, 713/1, 365/45, 463/45
• US Class Current: 711/152
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0739 in a data processing system embedded in automotive or aircraft systems
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G07C 2205/02 using a vehicle scan tool

Abstract

A method for computer memory calibration includes flashing a calibration from a processor into two flash memory sections. Either the same or an alternate processor requests data stored in one of the flash memory sections. Subsequently, exception handler logic within an exception mechanism activates and generates an exception for the data stored in the aforementioned flash memory section. The calibration in the other flash memory section then transfers to the processor through the functioning of the exception.

Claims

1. A computer calibration system, comprising:

a first memory section;

a second memory section;

an exception mechanism adapted to receive a request from a first central processing unit for first memory data from said first memory section, said exception mechanism containing logic operative to substantially prevent access to said first memory section, said exception mechanism further adapted to generate an exception signal as a function of said request, said exception mechanism adapted to transfer memory data from said second memory section as a function of said exception signal; and

an Engine Control Unit coupled to at least one of said first and second memory sections, said Engine Control Unit adapted to manage engine functions based on calibration values in one of said first and second memory sections.

2. The system of claim 1, wherein said Engine Control Unit includes an I/O port adapted for connection with a computing device capable of performing diagnostics.

3. The system of claim 1, wherein said Engine Control Unit includes an I/O port adapted for connection with a computing device, said Engine Control Unit being capable of storing new calibration data received from said I/O port.

4. A computer calibration system, comprising:

a first memory section;

a second memory section;

an exception mechanism adapted to receive a request from a first central processing unit for first memory data from said first memory section, said exception mechanism containing logic operative to substantially prevent access to said first memory section, said exception mechanism further adapted to generate an exception signal as a function of said request, said exception mechanism adapted to transfer memory data from said second memory section as a function of said exception signal;

a memory overlay, said memory overlay adapted to hold changes for said first and second memory sections; and

a second central processing unit containing logic adapted to control said memory overlay to hold changed for said first memory section.

5. The system of claim 4 wherein said memory overlay comprises a RAM overlay.

6. The system of claim 4 wherein said second central processing unit comprises a microcontroller containing said first and second flash memory sections and said memory overlay.

7. The system of claim 6 wherein said microcontroller has internal memory protection.

8. The system of claim 6 wherein said first central processing unit comprises a laptop.

9. The system of claim 6 wherein said first central processing unit comprises an external computing device.

10. The system of claim 4 wherein said first memory section comprises flash memory.

11. The system of claim 4 wherein said second memory section comprises flash memory.

12. The system of claim 4, further comprising a number of memory sections greater than two.

13. The system of claim 12 wherein flash memories comprise said number of memory sections greater than two.

14. A method for computer memory calibration, comprising:

flashing a calibration into a first flash memory section and a second flash memory section;

requesting that data stored in said first flash memory section transfer to a central processing unit;

activating exception handler logic within an exception mechanism;

generating an exception, through said exception handler logic;

for said data stored in said first flash memory section; and

transferring said calibration in said second flash memory section to said central processing unit as a function of said exception.

15. The method of claim 14 further comprising operating a memory overlay to modify said first flash memory section.

16. The method of claim 14 further comprising operating a memory resource to modify said first flash memory section.

17. The method of claim 14 wherein requesting further comprises requesting that data stored in said first flash memory section transfer to said central processing unit.

18. The method of claim 14 wherein flashing further comprises flashing a calibration into a plurality of flash memory sections.

19. A method for computer memory calibration, comprising:

flashing data from a processor into a first flash memory section and a second flash memory section;

sending a signal from said processor to modify said second flash memory section;

requesting that data stored in said first flash memory section transfer to a central processing unit;

activating exception handler logic within an exception mechanism;

generating an exception, through said exception handler logic, for said data stored in said first flash memory section; and

transferring said data in said second flash memory section to said central processing unit as a function of said exception.

20. The method of claim 19, wherein requesting further comprising requesting that data stored in said first flash memory section transfer to said central processing unit while said first flash memory is undergoing modification.

21. The method of claim 19 wherein flashing further comprises flashing data into a plurality of flash memory sections.