Multi-staged bios-based memory testing

• US 6,766,474 B2
• Filed: 12/21/2000
• Issued: 07/20/2004
• Est. Priority Date: 12/21/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Schelling, Todd A.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): Bonzo, Bryce P.
• Application Number:
  US09/745,974
• Publication Number:
  US 20020083369A1
• Time in Patent Office: 1,307 Days
• Field of Search: 714/30, 714/36, 714/42, 714/718, 713/2
• US Class Current: 714/36
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]

Abstract

The BIOS of a multiple processor system passes partial control to the operating system following an abbreviated power-on initialization. The BIOS program retains control of one or more processors and any memory that was untested during power-on. While the operating system is loaded and the system is operational, the BIOS program tests the retained memory. The BIOS program then relinquishes control of the retained memory and processor(s) during runtime to the operating system.

Claims

1. A method comprising:

passing control of at least one portion of a processor-based system to an operating system loaded on the processor-based system; and

retaining control of a second portion of the processor-based system by a power-on program,

retaining control of a second portion of the processor-based system further comprising retaining control of at least one processor of a plurality of processors.

2. The method of claim 1, retaining control of at least one processor of a plurality of processors further comprising:

identifying the plurality of processors available to the system in a table readable by the operating system;

notifying the operating system that the plurality of processors are available; and

declining to include the at least one processor in the table.

3. The method of claim 2, running both the power-on program and the operating system simultaneously further comprising;

executing the power-on program by the at least one processor of the plurality of processors; and

executing the operating system by a second processor, wherein the second processor is identified in the table.

4. A method comprising:

passing control of at least one portion of a processor-based system to an operating system loaded on the processor-based system;

retaining control of a second portion of the processor-based system by a power-on program;

running both the power-on program and the operating system program simultaneously;

retaining a portion of a memory by the power-on program;

performing memory operations on the retained portion of the memory by the power-on program while the operating system is running;

relinquishing a second portion of the memory to the operating system; and

performing memory operations on the relinquished portion of the memory by the operating system while the power-on program is running.

5. A method comprising:

passing control of at least one portion of a processor-based system to an operating system loaded on the processor-based system;

retaining control of a second portion of the processor-based system by a power-on program;

running both the power-on program and the operating system program simultaneously;

retaining a portion of a memory by the power-on program;

performing memory operations on the retained portion of the memory by the power-on program while the operating system is running;

performing memory operations on the retained portion of the memory by the power-on program while the operating system is running further comprising;

initializing the retained portion of memory; and

testing the retained portion of memory.

6. A system comprising:

a first storage to store a power-on program;

a second storage to store an operating system;

a first element controlled by the operating system;

a second element controlled by the power-on program,

wherein the first element is a first processor and the power-on program executes on the first processor,

wherein the second element is a second processor and the operating system executes on the second processor, and

a configuration table accessible to both the power-on routine and the operating system to identify the first element.

7. An article comprising a medium storing instructions to enable a processor-based system to:

pass control of at least one portion of the processor-based system to an operating system loaded on the processor-based system;

retain control of a second portion of the processor-based system by a power-on program;

run both the power-on program and the operating system program simultaneously;

retain a portion of a memory by the power-on program;

perform memory operations on the retained portion of the memory by the power-on program while the operating system is running;

relinquish a second portion of the memory to the operating system; and

perform memory operations on the relinquished portion of the memory by the operating system while the power-on program is running.

8. The article of claim 7, further storing instructions to enable a processor-based system to:

identify the plurality of processors available to the processor-based system in a table readable by the operating system;

notify the operating system that the plurality of processors are available; and

decline to include at least one processor of the plurality of processors in the table.

9. The article of claim 8, further storing instructions to enable a processor-based system to:

execute the power-on program by the at least one processor of the plurality of processors; and

execute the operating system by a second processor, wherein the second processor is identified in the table.

10. A system comprising:

two or more processors;

a device comprising a first portion and a second portion, wherein the device is coupled to the two or more processors; and

a power-on routine executable by one of the two or more processors, wherein the power-on routine relinquishes control of the first portion of the device before loading an operating system,

wherein the power-on routine further;

tests the second portion of the device while the operating system is running; and

relinquishes control of the second portion of the device to the operating system.

11. The system of claim 10, wherein the device is a memory.

12. The system of claim 10, wherein the device is a group of processors and the first portion of the device is a first processor and the second portion of the device is a second group of processors.

13. A system comprising:

two or more processors;

a device comprising a first portion and a second portion, wherein the device is coupled to the two or more processors;

an operating system executable by one of the two or more processors, wherein the operating system receives control of the first portion of the device when the operating system is executed; and

a power-on routine to relinquish control of the first portion of the device to the operating system,

wherein the operating system further;

receives an interrupt from the power-on routine; and

receives control of the second portion of the device.