CMOS imager with a self-aligned buried contact
First Claim
1. A method of forming a self-aligned buried contact in a CMOS imager, comprising the steps of:
- providing a substrate comprising at least one transistor and at least one isolation region, said substrate including a p-type well having only an n-doped region, said n-doped region formed in the p-type well by ion implantation;
forming a protective layer over said substrate;
selectively removing at least a portion of said protective layer between a gate of said at least one transistor and another substrate feature selected from the group consisting of another transistor gate and said isolation region, to form a self-aligned plug opening; and
forming a continuously conductive layer in said self-aligned plug opening to form a self-aligned buried contact.
2 Assignments
0 Petitions
Accused Products
Abstract
An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.
-
Citations
30 Claims
-
1. A method of forming a self-aligned buried contact in a CMOS imager, comprising the steps of:
-
providing a substrate comprising at least one transistor and at least one isolation region, said substrate including a p-type well having only an n-doped region, said n-doped region formed in the p-type well by ion implantation;
forming a protective layer over said substrate;
selectively removing at least a portion of said protective layer between a gate of said at least one transistor and another substrate feature selected from the group consisting of another transistor gate and said isolation region, to form a self-aligned plug opening; and
forming a continuously conductive layer in said self-aligned plug opening to form a self-aligned buried contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
-
-
29. A method of forming a self-aligned buried contact in a CMOS imager, comprising the steps of:
-
providing a silicon substrate comprising at least one transistor and at least one isolation region, said silicon substrate including a p-type well having an n-doped region and no n+ region;
forming a protective layer over said silicon substrate;
selectively removing by etching at least a portion of said protective layer between a gate of said at least one transistor and another substrate feature selected from the group consisting of another transistor gate and said isolation region, to form a self-aligned plus opening; and
forming a continuously conductive layer in said self-aligned plug opening to form a self-aligned buried contact.
-
-
30. A method of forming a self-aligned buried contact in a CMOS imager, comprising the steps of:
-
providing a silicon substrate comprising at least one transistor and at least one isolation region, said silicon substrate including a p-type well having an n-doped region and no n+ region, so as to reduce current leakage to said substrate;
forming a protective layer over said substrate;
selectively removing by etching at least a portion of said protective layer between a gate of said at least one transistor and another substrate feature selected from the group consisting of another transistor gate and said isolation region, to form a self-aligned plug opening; and
forming a continuously conductive layer in said self-aligned plug opening to form a self-aligned buried contact, said continuously conductive layer including no metallization layer directly in contact with the silicon substrate.
-
Specification