Semiconductor memory device with memory cells having same characteristics and manufacturing method for the same

• US 6,768,151 B2
• Filed: 01/17/2003
• Issued: 07/27/2004
• Est. Priority Date: 05/16/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Kasai, Naoki
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US10/346,071
• Publication Number:
  US 20030104674A1
• Time in Patent Office: 557 Days
• Field of Search: 257/295, 257/306, 257/310, 257/532, 438/3, 438/240
• US Class Current: 257/295
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region
• CPC Class Codes: H10B 53/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 53/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

In a method of manufacturing a semiconductor memory device, a lower electrode film is formed on a semiconductor substrate via an interlayer insulating film. A ferroelectric film is formed on the lower electrode layer while heating the lower electrode layer uniformly in the cell array region. An upper electrode film is formed on the ferroelectric film. Ferroelectric capacitors are formed in a memory cell array region. Each of the ferroelectric capacitors includes the lower electrode film, the ferroelectric film and the upper electrode film.

Claims

1. A semiconductor memory device having a memory cell array region, a peripheral circuit region and a connection region between said memory cell array region and said peripheral circuit region, comprising:

ferroelectric capacitors formed on a semiconductor substrate via an interlayer insulating film in said memory cell array region; and

conductive films formed on said interlayer insulating film in said connection regions

conductive routes passing through said interlayer insulating film in said connection region, each conductive route being connected with said conductive films and said semiconductor substrate, and

wherein both said conductive films and said conductive routes in said connection region are dummy structures.

2. The semiconductor memory device according to claim 1, further comprising MOS transistors formed on said semiconductor substrate in said memory cell array region and said connection region, and

wherein each of said ferroelectric capacitors is connected with one of said MOS transistors formed in said memory cell array region and each of said conductive films is connected with one of said MOS transistors formed in said connection regions,

wherein said MOS transistors formed in said connection region each includes a dummy gate electrode.

3. The semiconductor memory device according to claim 1, wherein a density of said ferroelectric capacitors is substantially the same as that of said conductive films.

4. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a logic circuit embedded FeRAM.

5. The semiconductor memory device according to claim 1, wherein each ferroelectric capacitor comprises lower electrode layer, a ferroelectric film, and an upper electrode layer, and

wherein the semiconductor memory device further comprises:

a second interlayer insulating film on said ferroelectric capacitors and said conductive films;

wiring lines on said second interlayer insulating film over at least said memory cell array region; and

contact plugs, respectively providing conductive paths through said second interlayer insulating film, from upper electrode layers of the ferroelectric capacitors to the wiring lines,

wherein no conductive paths through said second interlayer insulating film are provided for the conductive films formed in said connection region.

6. The semiconductor memory device according to claim 1, wherein the dummy structures further comprise additional conductive films, formed in said peripheral circuit region and connected with any of said conductive routes in said connection region.

7. The semiconductor memory device according to claim 1, wherein said peripheral circuit region comprise at least a sense amplifier.

8. The semiconductor memory device according to claim 1, wherein said peripheral circuit region comprise at least a line driver.

9. The semiconductor memory device according to claim 3, wherein in said connection region, in a direction orthogonal to said memory cell array regions and said peripheral circuit region, there are a plurality of said conductive films.

10. The semiconductor memory device according to claim 3, further comprising additional conductive routes in said memory cell array region, passing through said interlayer insulating film, each conductive route being connected with a respective ferroelectric capacitor and said semiconductor substrate,

wherein the conductive routes in the memory cell array region and the connection region have a substantially uniform density over the memory cell array region and the connection region.

11. The semiconductor memory device according to claim 10, wherein in said connection region, in a direction orthogonal to said memory cell array regions and said peripheral circuit region, there are a plurality of said conductive routes.

12. A semiconductor memory device having a memory cell array region, a peripheral circuit region and a connection region between said memory cell array region and said peripheral circuit region, comprising:

ferroelectric capacitors formed on a semiconductor substrate via an interlayer insulating film in said memory cell array region; and

conductive films formed on said interlayer insulating film in said connection region,

wherein said conductive films are connected with said semiconductor substrate via conductive routes passing through said interlayer insulating film, respectively, and

wherein a layer for said conductive films is formed when a lower electrode layer for said ferroelectric capacitors is formed.

13. The semiconductor memory device according to claim 12, wherein said lower electrode layer is formed of material containing at least one of platinum, iridium, iridium oxide, ruthenium and ruthenium oxide.

14. A semiconductor memory device having a memory cell array region, a peripheral circuit region and a connection region between said memory cell array region and said peripheral circuit region, comprising:

ferroelectric capacitors formed on a semiconductor substrate via an interlayer insulating film in said memory cell array region;

conductive films formed on said interlayer insulating film in said connection region; and

additional conductive films formed in said peripheral circuit region,

wherein said conductive films are connected with said semiconductor substrate via conductive routes passing through said interlayer insulating film, respectively, and

wherein said additional conductive films are connected with any of said conductive routes in said connection region.

15. A semiconductor memory device having a memory cell array region, a peripheral circuit region and a connection region between said memory cell array region and said peripheral circuit region comprising:

ferroelectric capacitors formed on a semiconductor substrate via an interlayer insulating film in said memory cell array region; and

conductive films formed on said interlayer insulating film in said connection region,

wherein said conductive films are connected with said semiconductor substrate via conductive routes passing through said interlayer insulating film, respectively, and

wherein said semiconductor memory device is a logic circuit embedded non-volatile SRAM.