Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system

• US 6,768,163 B2
• Filed: 09/25/2001
• Issued: 07/27/2004
• Est. Priority Date: 09/29/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sukegawa, Hiroshi, Tanaka, Tomoharu
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US09/961,355
• Publication Number:
  US 20020040990A1
• Time in Patent Office: 1,036 Days
• Field of Search: 257/296, 257/314, 257/315, 257/319, 257/700, 365/185.17, 365/185.08, 365/185.19, 365/194, 365/207, 365/208, 365/189.01, 365/185.21, 365/185.23, 365/185.24, 725/111, 725/109
• US Class Current: 257/319
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor integrated circuit device comprises a first semiconductor substrate and a second semiconductor substrate. A Memory cell array and word lines connected to the memory cell array each are provided in the first semiconductor substrate. A word line control circuit configured to control the word lines is provided in the second semiconductor substrate.

Claims

1. A semiconductor integrated circuit device comprising:

a first semiconductor substrate, in which, a memory cell array including a plurality of nonvolatile semiconductor memory cells, a plurality of bit lines electrically connected to the memory cell array, a plurality of word lines electrically connected to the memory cell array, a plurality of input terminals, and a plurality of transfer gate transistors each having one end electrically connected to a corresponding one of the word lines and another end electrically connected to a corresponding to one of the input terminals, are provided; and

a second semiconductor substrate, in which, a plurality of output terminals electrically connected to the input terminals of the first semiconductor substrate, and a word line control circuit configured to control the word lines and electrically connected to the output terminals, are provided.

2. The device according to claim 1, wherein the second semiconductor substrate stacked on the first semiconductor substrate.

3. The device according to claim 1, further comprising:

a plurality of first semiconductor substrates, wherein the second semiconductor substrate stacked on at least one of the plurality of first semiconductor substrates.

4. The device according to claim 1, further comprising:

a first package which seals the first semiconductor substrate, the first package having a plurality of first terminals electrically connected to the input terminals of the first semiconductor substrate, the first terminals being provided on a side surface of the first package;

a second package which seals the second semiconductor substrate, the second package having a plurality of second terminals electrically connected to the output terminals of the second semiconductor substrate, the second terminals being provided on a side surface of the second package; and

a plurality of wirings which electrically connects the first terminals of the first package and the second terminals of the second package, the wirings being provided on the side surfaces of the first package and the second package.

5. The device according to claim 4, wherein the second package is stacked on a surface different from the side surface of the first package.

6. The device according to claim 4, further comprising:

a plurality of first packages,

wherein the second package stacked on a surface different from the side surface of at least one of the first packages.

7. The device according to claim 4, further comprising:

a third package which seals the first package, the second package and the wirings.

8. The device according to claim 6, further comprising:

a third package which seals the first packages, the second package and the wirings.

9. A semiconductor integrated circuit device comprising:

a first semiconductor substrate, in which, a memory cell array including a plurality of nonvolatile semiconductor memory cells, a plurality of bit lines electrically connected to the memory cell array, a plurality of word lines electrically connected to the memory cell array, a plurality of input terminals, and a plurality of transfer gate transistors each having one end electrically connected to a corresponding one of the word lines and another end electrically connected to a corresponding to one of the input terminals, are provided; and

a second semiconductor substrate, in which, a plurality of output terminals electrically connected to the input terminals of the first semiconductor substrate, and a word line control circuit configured to control the word lines and electrically connected to the output terminals, an interface circuit, and a plurality of interface terminals electrically connected to the interface circuit, are provided.

10. The device according to claim 9, further comprising:

a first package which seals the first semiconductor substrate, the first package having a plurality of first terminals electrically connected to the input terminals of the first semiconductor substrate, the first terminals being provided on a side surface of the first package,

a second package which seals the second semiconductor substrate, the second package having a plurality of second terminals electrically connected to the output terminals of the second semiconductor substrate, and a plurality of third terminals electrically connected to the interface terminals of the second semiconductor substrate, the second terminals being provided on a side surface of the second package and the third terminals being provided on a side surface of the second package opposite to a lamination surface with the first package; and

a plurality of wirings which electrically connects the first terminals of the first package and the second terminals of the second package, the wirings being provided on the side surfaces of the first package and the second package.

11. The device according to claim 10, wherein the second package stacked on a surface different from the side surface of the first package.

12. The device according to claim 10, further comprising:

a plurality of first packages,

wherein the second package stacked on a surface different from the side surface of at least one of the first packages.

13. The device according to claim 10, further comprising:

a third package which seals the first package, the second package and the wiring, the third package having a plurality of fourth terminals electrically connected to the third terminals of the second package.

14. The device according to claim 12, further comprising:

a third package which seals the first packages, the second package and the wirings, the third package having a plurality of fourth terminals electrically connected to the third terminals of the second package.

15. A semiconductor integrated circuit device comprising:

a first semiconductor substrate, in which, a memory cell array including a plurality of nonvolatile semiconductor memory cells, a plurality of bit lines electrically connected to the memory cell array, a first shift register configured to control the bit lines, a plurality of word lines electrically connected to the memory cell array, a plurality of input terminals, a plurality of transfer gate transistors each having one end electrically connected to a corresponding one of the word lines and another end electrically connected to a corresponding to one of the input terminals, and a second shift register configured to control the transfer gate transistors, are provided; and

a second semiconductor substrate, in which, a plurality of output terminals electrically connected to the input terminals of the first semiconductor substrate, and a word line control circuit configured to control the word lines and electrically connected to the output terminals, are provided.

16. The device according to claim 15, wherein the second semiconductor substrate stacked on the first semiconductor substrate.

17. The device according to claim 15, further comprising:

a plurality of first semiconductor substrates, wherein the second semiconductor substrate is stacked on at least one of the plurality of first semiconductor substrates.

18. The device according to claim 15, wherein the second semiconductor substrate, in which, a storage circuit which stores an address of a defected memory cell in the memory cell array.

19. A nonvolatile semiconductor memory device comprising:

a first semiconductor substrate, in which, a memory having a memory cell array including a plurality of nonvolatile semiconductor memory cells, is provided; and

a second semiconductor substrate, in which, a control portion configured to control the memory, a network interface connectable to a network, a file management portion connected to the network interface configured to manages a relation between a data file given from the network and an address of the memory cell array, and a memory interface connected to the file management portion configured to convert a signal given from the network to a signal which capable is of used at the control portion, are provided.

20. The device according to claim 19, wherein the second semiconductor substrate stacked on the first semiconductor substrate.

21. The device according to claim 19, further comprising:

a plurality of first semiconductor substrates, wherein the second semiconductor substrate is stacked on at least one of the plurality of first semiconductor substrates.

22. The device according to claim 19, further comprising:

a first package which seals the first semiconductor substrate, the first package having a plurality of first terminals electrically connected to the memory cell array, the first terminals being provided on a side surface of the first package; and

a second package which seals the second semiconductor substrate, the second package having a plurality of second terminals electrically connected to the memory interface, and a plurality of third terminals electrically connected to the network interface, the second terminals being provided on a side surface of the second package and the third terminals being provided on a surface of the second package opposite to a lamination surface with the first package;

a plurality of wirings which electrically connects the first terminals of the first package and the second terminals of the second package, the wirings being provided on the side surfaces of the first package and the second package.

23. The device according to claim 22, wherein the second package stacked on a surface different from the side surface of the first package.

24. The device according to claim 22, further comprising:

a plurality of first packages,

wherein the second package stacked on a surface different from the side surface of at least one of the first packages.

25. The device according to claim 22, further comprising:

a third package which seals the first package, the second package and the wiring, the third package having a plurality of fourth terminals electrically connected to the third terminals of the second package.

26. The device according to claim 24, further comprising:

a third package which seals the first packages, the second package and the wirings, the third package having a plurality of fourth terminals electrically connected to the third terminals of the second package.