High-voltage transistor with JFET conduction channels

• US 6,768,171 B2
• Filed: 05/02/2002
• Issued: 07/27/2004
• Est. Priority Date: 11/27/2000
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US10/137,762
• Publication Number:
  US 20020132406A1
• Time in Patent Office: 817 Days
• Field of Search: 257/262
• US Class Current: 257/342
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises a first buried layer disposed in a first epitaxial layer formed on a substrate, a second buried layer disposed in a second epitaxial layer formed on the first epitaxial layer, with the first and second buried layers being spaced vertically apart in a substantially parallel configuration such that a JFET conduction channel of the first conductivity type is formed between the first and second buried layers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Claims

1. A high-voltage field-effect transistor (HVFET) comprising:

a first buried layer of a second conductivity type disposed in a first epitaxial layer of a first conductivity type;

a second buried layer of the second conductivity type disposed in a second epitaxial layer of the first conductivity type, the one or more first and second buried layers being spaced vertically apart in a substantially parallel configuration such that a JFET conduction channel of the first conductivity type is formed between the first and second buried layers;

a drain region of the first conductivity type disposed in the second epitaxial layer;

a body region of the second conductivity type disposed in the second epitaxial layer;

a source region of the first conductivity type disposed in the body region; and

an insulated gate member disposed adjacent to the body region; and

wherein the first epitaxial layer is formed on a substrate of the second conductivity type.

2. The HVFET of claim 1 wherein the first buried layer is spaced apart from an upper surface of the substrate.

4. The HVFET of claim 1 further comprising an isolation dielectric region that extends vertically from the upper surface of the second epitaxial layer to the substrate.

3. A high-voltage field-effect transistor (HVFET) comprising;

a first buried layer of a second conductivity type disposed in a first epitaxial layer of a first conductivity type;

a second buried layer of the second conductivity type disposed in a second epitaxial layer of the first conductivity type, the first and second buried layers being spaced vertically apart in a substantially parallel configuration such that a JFET conduction channel of the first conductivity type is formed between the first and second buried layers;

a drain region of the first conductivity type disposed in the second epitaxial layer;

a body region of the second conductivity type disposed in the second epitaxial layer;

a source region of the first conductivity type disposed in the body region; and

an insulated gate member disposed adjacent to the body region,

wherein the insulated gate member comprises a trench gate structure.

5. A high-voltage field-effect transistor (HVFET) comprising:

a well region of a first conductivity disposed in a substrate of a second conductivity type;

a first buried layer of the second conductivity type disposed in the well region;

an epitaxial layer of the first conductivity type formed on the substrate;

a second buried layer of the second conductivity type disposed in the epitaxial layer, the first and second buried layers being spaced vertically apart in a substantially parallel configuration such that a JFET conduction channel of the first conductivity type is formed between the first and second buried layers;

a drain region of the first conductivity type disposed in the epitaxial layer;

a body region of the second conductivity type disposed in the epitaxial layer;

a source region of the first conductivity type disposed in the body region; and

an insulated gate member disposed adjacent to the body region.

6. The HVFET of claim 5 wherein the first buried layer is spaced apart from the substrate.

7. The HVFET of claim 5 wherein the second buried layer is spaced apart from the upper surface of the epitaxial layer.

8. The HVFET of claim 5 wherein the first conductivity type is N-type and the second conductivity type is P-type.

9. The HVFET of claim 5 wherein the insulated gate member comprises a trench gate structure.

10. The HVFET of claim 5 wherein the insulated gate member comprises a planar gate structure.

11. The HVFET of claim 5 further comprising an isolation region of the second conductivity type that extends vertically from the body region to the substrate.

12. The HVFET of claim 5 further comprising:

a drain electrode electrically connected to the drain region;

a source electrode electrically connected to the source region.

13. The HVFET of claim 5 further comprising an isolation dielectric region disposed adjacent the body region and extending vertically from the upper surface of the epitaxial layer to the substrate.

14. A high-voltage field-effect transistor (HVFET) comprising:

a substrate of a second conductivity type;

a first epitaxial layer of a first conductivity type disposed on the substrate;

a first plurality of buried layers of the second conductivity type disposed in the first epitaxial layer such that a first plurality of JFET conduction channels is formed in the first epitaxial layer;

a second epitaxial layer of the first conductivity type;

a second plurality of buried layers of the second conductivity type disposed in the second epitaxial layer such that a second plurality of JFET conduction channels is formed in the second epitaxial layer;

a drain region of the first conductivity type disposed in the second epitaxial layer;

a body region of the second conductivity type disposed in the second epitaxial layer;

a source region of the first conductivity type disposed in the body region; and

an insulated gate member disposed adjacent to the body region.

15. The HVFET of claim 14 wherein a lowermost one of the first plurality of buried layers is spaced apart from the substrate.

16. The HVFET of claim 14 wherein a lowermost one of the second plurality of buried layers is spaced apart from the upper surface of the first epitaxial layer.

17. The HVFET of claim 14 wherein the first conductivity type is N-type and the second conductivity type is P-type.

18. The HVFET of claim 14 wherein the insulated gate member comprises a trench gate structure.

19. The HVFET of claim 14 wherein the insulated gate member comprises a planar gate structure.

20. The HVFET of claim 14 further comprising an isolation region of the second conductivity type that extends vertically from the body region to the substrate.

21. The HVFET of claim 14 further comprising:

a drain electrode electrically connected to the drain region;

a source electrode electrically connected to the source region.

22. The HVFET of claim 14 further comprising an isolation dielectric region disposed adjacent the body region and extending vertically from the upper surface of the second epitaxial layer to the substrate.

23. The HVFET of claim 14 wherein the second plurality of buried layers is spaced-apart from the body region.

24. A high-voltage field-effect transistor (HVFET) comprising:

a well region of a first conductivity type disposed in a substrate of a second conductivity type;

a first plurality of buried layers of a second conductivity type disposed within the well region such that a first plurality of JFET conduction channels is formed in the well region;

an epitaxial layer of the first conductivity type;

a second plurality of buried layers of the second conductivity type disposed in the epitaxial layer such that a second plurality of JFET conduction channels is formed in the epitaxial layer;

a drain region of the first conductivity type disposed in the epitaxial layer;

a body region of the second conductivity type disposed in the epitaxial layer;

a source region of the first conductivity type disposed in the body region; and

an insulated gate member disposed adjacent to the body region.

25. The HVFET of claim 24 wherein a lowermost one of the first plurality of buried layers is spaced apart from the substrate.

26. The HVFET of claim 24 wherein a lowermost one of the second plurality of buried layers is spaced apart from the upper surface of the substrate.

27. The HVFET of claim 24 wherein the first conductivity type is N-type and the second conductivity type is P-type.

28. The HVFET of claim 24 wherein the insulated gate member comprises a trench gate structure.

29. The HVFET of claim 24 wherein the insulated gate member comprises a planar gate structure.

30. The HVFET of claim 24 further comprising an isolation region of the second conductivity type that extends vertically from the body region to the substrate.

31. The HVFET of claim 24 further comprising:

a drain electrode electrically connected to the drain region;

a source electrode electrically connected to the source region.

32. The HVFET of claim 24 further comprising an isolation dielectric region disposed adjacent the body region and extending vertically from the upper surface of the epitaxial layer to the substrate.

33. An extended drain region of a high-voltage field-effect transistor (HVFET) comprising:

a first epitaxial layer of a first conductivity type disposed on a substrate of a second conductivity type;

one or more first buried layers of the second conductivity type disposed in the first epitaxial layer;

one or more second buried layers of the second conductivity type disposed in a second epitaxial layer of the first conductivity type, the one or more first and the one or more second buried layers being spaced vertically apart in a substantially parallel configuration so as to form one or more JFET conduction channels of the first conductivity type.

34. The extended drain region of claim 33 wherein the one or more first buried layers are spaced apart from an upper surface of the substrate.

35. The extended drain region of claim 33 wherein the one or more second buried layers are spaced apart from the upper surface of the second epitaxial layer.

36. The extended drain region of claim 33 wherein the first conductivity type is N-type and the second conductivity type is P-type.

37. An extended drain region of a high-voltage field-effect transistor (HVFET) comprising:

a well region of a first conductivity disposed in a substrate of a second conductivity type;

one or more first buried layers of the second conductivity type disposed in the well region;

an epitaxial layer of the first conductivity type formed on the substrate layer;

one or more second buried layers of the second conductivity type disposed in the epitaxial layer, the one or more first and the one or more second buried layers being spaced vertically apart in a substantially parallel configuration so as to form one or more JFET conduction channels of the first conductivity type.

38. The HVFET of claim 37 wherein the one or more first buried layers are spaced apart from the substrate.

39. The HVFET of claim 37 wherein the one or more second buried layers are spaced apart from the upper surface of the epitaxial layer.

40. The HVFET of claim 37 wherein the first conductivity type is N-type and the second conductivity type is P-type.