Stack type flip-chip package

• US 6,768,190 B2
• Filed: 04/23/2002
• Issued: 07/27/2004
• Est. Priority Date: 01/25/2002
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Wang, Hsueh-Te, Yang, Chaur-Chin
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US10/128,719
• Publication Number:
  US 20030141582A1
• Time in Patent Office: 826 Days
• Field of Search: 257/723, 257/685, 257/686, 257/777, 257/778, 257/773, 257/784, 257/690, 257/691, 257/737, 257/738, 257/676, 257/779, 257/684, 257/787
• US Class Current: 257/686
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stack type flip-chip package that utilizes a redistribution circuit on the back of a chip to serve as a bridge for connecting with other chips. The package includes at least a substrate, a first chip, a second chip, some underfill material and some packaging material. The substrate has a plurality of bump contacts and a plurality of line contacts thereon. The first chip has an active surface with a plurality of first bonding pads thereon. The back surface of the first chip has a redistribution circuit. The redistribution circuit has a plurality of bump pads and a plurality of line pads thereon. The second chip has an active surface with a plurality of second bonding pads thereon. Bumps are positioned between the bump contacts and the first bonding pads and between the bump pads and the second bonding pads. Conductive wires connect the line contacts and the line pads. The underfill material fills the space between the chip and the substrate and the gap between the first and the second chips. The packaging material encloses the chips and the conductive wires.

Claims

1. A stack type flip-chip package, comprising:

a substrate board having a surface with a plurality of bump contacts and a plurally of line contacts thereon;

a first chip having a first active surface and a back surface, wherein the first active surface has a plurality of first bonding pads thereon;

a redistribution circuit layer on the back surface of the first chip, wherein the redistribution circuit layer has a plurality of bump pads and a plurality of line pads thereon;

a passivation layer on the back surface of the first chip, exposing the bump pads and the line pads of the redistribution circuit layer;

a second chip having a second active surface with a plurality of second bonding pads thereon;

a plurality of bumps, wherein a portion of the bumps are disposed between the bump contacts and the first bonding pads, and a portion of the bumps are disposed between the bump pads and the second bonding pads;

a plurality of conductive wires for connecting between the line contacts and the line pads;

a packaging material, used for enclosing the first chip, the second chip and the conductive wires; and

an underfill material filling the space between the first chip and the substrate and filling the gap between the first chip and the second chip.

2. A stack type flip-chip package, comprising:

a substrate having a surface with a plurality of bump contacts and a plurality of line contacts thereon;

a first chip having a first active surface and a back surface, wherein the first active surface has a plurality of first bonding pads thereon;

a redistribution circuit layer on the back surface of the first chip, wherein tho redistribution circuit layer has a plurality of bump pads and a plurality of line pads thereon;

a passivation layer on the back surface of the first chip, exposing the bump pads and the line pads of the redistribution circuit layer;

a plurality of second chips each having a second active surface with a plurality of second bonding pads thereon;

a plurality of bumps, wherein a portion of the bumps are disposed between the bump contacts and the first bonding pads and a portion of the bumps are disposed between the bump pads and the second bonding pads;

a plurality of conductive wires for connecting between the line contacts and the line pads;

a packaging material for enclosing the first chip, the second chips and the conductive wires; and

an underfill material filling the space between the first chip and the substrate and filling the gaps between the first chip and the second chips.

3. A stack type flip-chip package, comprising:

a substrate having a surface with a plurality of bump contacts and a plurality of line contacts thereon;

a first chip having a first active surface and a back surface, wherein the first active surface has a plurality of first bonding pads thereon;

a first redistribution circuit layer on the back surface of the first chip, wherein the redistribution circuit layer has a plurality of first bump pads and a plurality of first line pads thereon;

a first passivation layer on the back surface of the first chip, exposing the first bump pads and the first line pads of the first redistribution circuit layer;

a plurality of second chips each having a second active surface with a plurality of second bonding pads thereon;

a plurality of second redistribution circuit layers on the back surfaces of the second chips, wherein each second redistribution circuit layer has a plurality of second bump pads and a plurality of second line pads thereon;

a plurality of second passivation layers on the back surfaces of the second chips, exposing the second bump pads and the second line pads of the second redistribution circuit layers;

at least one third chip having a third active surface with a plurality of third bonding pads thereon;

a plurality of bumps disposed between the bump contacts and the first bonding pads, disposed between the second bonding pads and the first bump pads, and disposed between the second bump pads and the third bonding pads;

a plurality of conductive wires for connecting between the line contacts and the first line pads, and connecting between the second line pads and the first line pads;

a packaging material for enclosing the first chip, the second chips, the third chip and the conductive wires; and

an underfill material filling the space between the first chip and the substrate, filling the gap between the first chip and the second chip, and filling the gap between the second chip and the third chip.