Voltage controlled oscillator and PLL circuit using the same

• US 6,768,387 B1
• Filed: 08/08/2000
• Issued: 07/27/2004
• Est. Priority Date: 03/08/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamashita, Hiroki, Masuda, Noboru
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/634,544
• Time in Patent Office: 1,449 Days
• Field of Search: 331/57, 331/179, 331/36.C, 331/34, 331/11
• US Class Current: 331/57
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

The present invention relates to a PLL circuit and a voltage controlled oscillator wherein a clock signal jitter caused when the supply voltage fluctuates of which is small can be supplied, and the voltage controlled oscillator is provided with a MOS transistor to one end of which a first power source (Vss) is connected and to the gate electrode of which a control signal for controlling the oscillation frequency is input, an oscillator connected between the other end of the MOS transistor and a second power source (Vdd) and a capacitative element connected to the oscillator in parallel and is further provided with additive control means for minutely controlling the oscillation frequency.

Claims

1. A voltage controlled oscillator circuit, comprising:

a first node connected to a first power source having a first voltage;

a second node connected to a second power source having a second voltage;

a first MOS transistor;

an oscillator arranged between the first node and a third node; and

a first capacitive element arranged between the first node and the third node;

a second capacitive element; and

a node connected to the second capacitive element;

wherein an oscillation frequency of the oscillator is controlled by connecting a source of the first MOS transistor to the second node, connecting a drain of the first MOS transistor to the third node, applying an analog control signal to a gate of the first MOS transistor, and changing a frequency of a high level and a low level of a digital control signal; and

connection to and disconnection from the second capacitive element are selected according to the digital control signal.

2. A voltage controlled oscillator circuit according to claim 1, wherein the oscillator includes at least three inverters each formed by connecting a drain of a P-channel MOS transistor to a drain of an N-channel MOS transistor;

and

wherein the inverters are looped by sequentially connecting respective output terminals of the inverters to respective input terminals of the inverters.

3. A phase-locked loop (PLL) circuit, comprising:

a voltage controlled oscillator circuit according to claim 2;

a frequency divider;

a phase comparator;

a frequency comparator; and

a control circuit;

wherein the frequency divider outputs a divided output signal obtained by dividing a frequency of an output signal from the voltage controlled oscillator circuit;

wherein the phase comparator receives a reference signal and the divided output signal, compares a phase of the reference signal with a phase of the divided output signal, and outputs a phase difference detection signal;

wherein the frequency comparator receives the reference signal and the divided output signal, compares a frequency of the reference signal with a frequency of the divided output signal, and outputs a frequency difference detection signal;

wherein the control circuit receives the phase difference detection signal and the frequency difference detection signal and outputs the analog control signal to execute control according to the phase difference detection signal and the frequency difference detection signal; and

wherein the phase difference detection signal corresponds to the digital control signal.

4. A phase-locked loop (PLL) circuit according to claim 3, wherein the control circuit also receives the reference signal;

wherein the control circuit executes control according to the phase difference detection signal and the frequency difference detection signal every cycle of the reference signal; and

wherein a variation of a voltage of the analog control signal according to the frequency difference detection signal is larger than a variation of the voltage of the analog control signal according to the phase difference detection signal.

5. A phase-locked loop (PLL) circuit according to claim 3, wherein the control circuit has a control cycle in which the control circuit executes control according to the phase difference detection signal and the frequency difference detection signal every cycle of the reference signal;

and

wherein the frequency comparator includes

means for comparing the frequency of the reference signal with the frequency of the divided output signal, and

means for preventing a variation of a voltage of the analog control signal according to the phase difference detection signal in a first control cycle in which the frequency difference detection signal corresponding to a detection of a frequency difference is outputted and in a predetermined number of control cycles following the first control cycle.

6. A phase-locked loop (PLL) circuit, comprising:

a voltage controlled oscillator circuit according to claim 1;

a frequency divider;

a phase comparator;

a frequency comparator; and

a control circuit;

wherein the frequency divider outputs a divided output signal obtained by dividing a frequency of an output signal from the voltage controlled oscillator circuit;

wherein the phase comparator receives a reference signal and the divided output signal, compares a phase of the reference signal with a phase of the divided output signal, and outputs a phase difference detection signal;

wherein the frequency comparator receives the reference signal and the divided output signal, compares a frequency of the reference signal with a frequency of the divided output signal, and outputs a frequency difference detection signal;

wherein the control circuit receives the phase difference detection signal and the frequency difference detection signal and outputs the analog control signal to execute control according to the phase difference detection signal and the frequency difference detection signal; and

wherein the phase difference detection signal corresponds to the digital control signal.

7. A phase-locked loop (PLL) circuit according to claim 6, wherein the control circuit also receives the reference signal;

wherein the control circuit executes control according to the phase difference detection signal and the frequency difference detection signal every cycle corresponding to one cycle of the reference signal; and

wherein a variation of a voltage of the analog control signal according to the frequency difference detection signal is larger than a variation of the voltage of the analog control signal according to the phase difference detection signal.

8. A phase-locked loop (PLL) circuit according to claim 6, wherein the control circuit has a control cycle in which the control circuit executes control according to the phase difference detection signal and the frequency difference detection signal every cycle of the reference signal;

and

wherein the frequency comparator includes

means for comparing the frequency of the reference signal with the frequency of the divided output signal, and

means for preventing a variation of a voltage of the analog control signal according to the phase difference detection signal in a first control cycle in which the frequency difference detection signal corresponding to a detection of a frequency difference is outputted and in a predetermined number of control cycles following the first control cycle.

9. A voltage controlled oscillator circuit, comprising:

a first node connected to a first power source having a first voltage;

a second node connected to a second power source having a second voltage;

a first MOS transistor;

an oscillator arranged between the first node and a third node; and

a first capacitive element arranged between the first node and the third node;

a second capacitive element; and

a second MOS transistor;

wherein an oscillation frequency of the oscillator is controlled by connecting a source of the first MOS transistor to the second node, connecting a drain of the first MOS transistor to the third node, applying an analog control signal to a gate of the first MOS transistor, and changing a frequency of a high level and a low level of a digital control signal;

the second MOS transistor is used for a switch to the second capacitive element; and

connection to and disconnection from the second capacitive element are selected by inputting the digital control signal to a gate of the second MOS transistor.

10. A voltage controlled oscillator according to claim 9, wherein the oscillator includes at least three inverters each formed by connecting a drain of a P-channel MOS transistor to a drain of an N-channel MOS transistor;

and

wherein the inverters are looped by sequentially connecting respective output terminals of the inverters to respective input terminals of the inverters.

11. A phase-locked loop (PLL) circuit, comprising:

a voltage controlled oscillator circuit according to claim 10;

a frequency divider;

a phase comparator;

a frequency comparator; and

a control circuit;

wherein the frequency divider outputs a divided output signal obtained by dividing a frequency of an output signal from the voltage controlled oscillator circuit;

wherein the phase comparator receives a reference signal and the divided output signal, compares a phase of the reference signal with a phase of the divided output signal, and outputs a phase difference detection signal;

wherein the frequency comparator receives the reference signal and the divided output signal, compares a frequency of the reference signal with a frequency of the divided output signal, and outputs a frequency difference detection signal;

wherein the control circuit receives the phase difference detection signal and the frequency difference detection signal and outputs the analog control signal to execute control according to the phase difference detection signal and the frequency difference detection signal; and

wherein the phase difference detection signal corresponds to the digital control signal.

12. A phase-locked loop (PLL) circuit according to claim 11, wherein the control circuit also receives the reference signal;

wherein the control circuit executes control according to the phase difference detection signal and the frequency difference detection signal every cycle of the reference signal; and

wherein a variation of a voltage of the analog control signal according to the frequency difference detection signal is larger than a variation of the voltage of the analog control signal according to the phase difference detection signal.

13. A phase-locked loop (PLL) circuit according to claim 11, wherein the control circuit has a control cycle in which the control circuit executes control according to the phase difference detection signal and the frequency difference detection signal every cycle of the reference signal;

and

wherein the frequency comparator includes

means for comparing the frequency of the reference signal with frequency of the divided output signal, and

means for preventing a variation of a voltage of the analog control signal according to the phase difference detection signal in a first control cycle in which the frequency difference detection signal corresponding to a detection of a frequency difference is outputted and in a predetermined number of control cycles following the first control cycle.

14. A phase-locked loop (PLL) circuit, comprising:

a voltage controlled oscillator circuit according to claim 9;

a frequency divider;

a phase comparator;

a frequency comparator; and

a control circuit;

wherein the frequency divider outputs a divided output signal obtained by dividing a frequency of an output signal from the voltage controlled oscillator circuit;

wherein the phase comparator receives a reference signal and the divided output signal, compares a phase of the reference signal with a phase of the divided output signal, and outputs a phase difference detection signal;

wherein the frequency comparator receives the reference signal and the divided output signal, compares a frequency of the reference signal with a frequency of the divided output signal, and outputs a frequency difference detection signal;

wherein the control circuit receives the phase difference detection signal and the frequency difference detection signal and outputs the analog control signal to execute control according to the phase difference detection signal and the frequency difference detection signal; and

wherein the phase difference detection signal corresponds to the digital control signal.

15. A phase-locked loop (PLL) circuit according to claim 14, wherein the control circuit also receives the reference signal;

wherein the control circuit executes control according to the phase difference detection signal and the frequency difference detection signal every cycle corresponding to one cycle of the reference signal; and

wherein a variation of a voltage of the analog control signal according to the frequency difference detection signal is larger than a variation of the voltage of the analog control signal according to the phase difference detection signal.

16. A phase-locked loop (PLL) circuit according to claim 14, wherein the control circuit has a control cycle in which the control circuit executes control according to the phase difference detection signal and the frequency difference detection signal every cycle of the reference signal;

and

wherein the frequency comparator includes

means for comparing the frequency of the reference signal with the frequency of the divided output signal, and

means for preventing a variation of a voltage of the analog control signal according to the phase difference detection signal in a first control cycle in which the frequency difference detection signal corresponding to a detection of a frequency difference is outputted and in a predetermined number of control cycles following the first control cycle.