Exposure control circuit for solid-state imaging apparatus

• US 6,768,511 B1
• Filed: 01/31/2000
• Issued: 07/27/2004
• Est. Priority Date: 02/01/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakakuki, Toshio, Nakai, Tomomichi
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Villecco, John M
• Application Number:
  US09/495,419
• Time in Patent Office: 1,639 Days
• Field of Search: 348/223.1, 348/225.1, 348/226.1, 348/228.1, 348/229.1, 348/230.1, 348/312, 348/362, 348/296, 358/516, 358/518, 358/520
• US Class Current: 348/229.1
• CPC Class Codes: H04N 23/72 Combination of two or more compensation controls

Abstract

A solid-state imaging apparatus having a CCD image capturing circuit includes an exposure time control circuit which analyzes the image signal generated by the image capturing circuit and generates a control signal to adjust an image exposure time. A balance control circuit also receives the control signal and updates gain control information used by an image processing circuit that generates color difference data (U/V data) from the image signal.

Claims

1. A solid-state imaging apparatus comprising:

a solid-state imaging device for accumulating information charges corresponding to an image of a sensed object and generating an image signal consisting of a plurality of color components;

a drive circuit connected to the solid-state imaging device to drive the solid-state imaging device so that the image signal is generated within a predetermined time period;

a timing control circuit connected to the drive circuit to provide a timing signal to the drive circuit, wherein the timing signal determines a length of the predetermined time period;

an exposure control circuit, connected to the imaging device and the timing control circuit, to determine an exposure state of the imaging device based on the image signal in a first cycle and control the timing control circuit in order to shorten or lengthen the predetermined time period; and

a white balance circuit, connected to the imaging device and the exposure control circuit, to perform a predetermined process on the plurality of color components of the image signal in a second cycle, which is longer than the first cycle, so that the plurality of color components are relatively balanced with one another, wherein the white balance circuit performs the predetermined process in a third cycle that is shorter than the second cycle when the exposure control circuit determines that the exposure state is stable.

2. The solid state imaging apparatus according to claim 1, wherein the third cycle is the same as the first cycle.

3. The solid-state imaging apparatus according to claim 1, wherein the solid-state imaging device generates the image signal in correspondence with a screen during the predetermined time period, and wherein the exposure control circuit includes:

an integrating circuit for integrating the image signal screen by screen to generate an integrated value;

a comparing circuit connected to the integrating circuit to compare the integrated value with an upper limit value and a lower limit value of an appropriate exposure state in order to generate a comparison signal; and

a determination circuit connected to the comparing circuit to activate one of a lengthening signal, a shortening signal, and a hold signal, wherein the determination circuit activates the shortening signal when the integrated value is higher than the upper limit value, the lengthening signal when the integrated value is lower than the lower limit value, and the hold signal when the integrated value is between the upper and lower limit values.

4. The solid state imaging apparatus according to claim 3, wherein the white balance circuit performs the predetermined process in the third cycle when the hold signal from the determination circuit is activated.

5. The solid-state imaging apparatus according to claim 3, wherein the predetermined process includes applying a gain to the plurality of color components of the image signal, and wherein the white balance circuit includes:

a plurality of integrating circuits for generating a plurality of integrated values by integrating each of the plurality of color components of the image signal;

a computation circuit connected to the plurality of integrating circuits to generate a plurality of gains that are selectively applied to the plurality of color components from the plurality of integrated values; and

a plurality of latch circuits connected to the computation circuit to hold the plurality of gains.

6. The solid-state imaging apparatus according to claim 5, wherein the white balance circuit further includes a decoder connected to the plurality of latch circuits to generate a reset signal having a predetermined cycle set in response to the hold signal from the determination circuit, wherein the reset signal resets the plurality of latches so that the plurality of gains are recalculated.

7. The solid-state imaging apparatus according to claim 6, wherein the plurality of integrating circuits generate the plurality of integrated values in accordance with the reset signal.