Low-voltage-triggered SOI-SCR device and associated ESD protection circuit

• US 6,768,619 B2
• Filed: 02/13/2003
• Issued: 07/27/2004
• Est. Priority Date: 07/09/2001
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Ker, Ming-Dou, Huang, Shao-Chang, Hung, Kei-Kang
• Primary Examiner(s): LEJA, RONALD W
• Application Number:
  US10/367,502
• Publication Number:
  US 20030122192A1
• Time in Patent Office: 530 Days
• Field of Search: 361/56, 361/91.1, 361/91.5, 361/111, 361/119, 257/107, 257/119, 257/146, 257/147, 257/162, 257/173, 257/355-360, 257/365
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Abstract

A silicon-on-insulator low-voltage-triggered silicon controlled rectifier device structure that is built upon a substrate and an insulation layer. The insulation layer has a plurality of isolation structures thereon to define a device region. A first-type well and a second-type well are formed over the insulation layer. The first-type and second-type wells are connected. A first gate and a second gate are formed over the first-type well and the second-type well, respectively. The first-type well further includes a first second-type doped region and a first first-type doped region formed between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region together form a cathode of the SOI-SCR device. A second first-type doped region is formed within the first-type well between the first second-type doped region and the first gate structure adjacent to the first second-type doped region. A third first-type doped region is formed within the first and the second-type well around their junction between the first and second-type well. The second-type well further includes a second second-type doped region and a fourth first-type doped region within the second-type well between the second second-type doped region and the second gate adjacent to the second second-type doped region. The second second-type doped region and the fourth first-type doped region together form an anode of the SOI-SCR device.

Claims

1. An electrostatic discharge (ESD) protection circuit having a silicon-on-insulator (SOI) silicon controlled rectifier (SCR) device thereon for coupling with an input/output pad and an internal circuit, wherein the ESD circuit includes:

an SOI-SCR device having a cathode, an anode, a first gate and a second gate, wherein the cathode connects electrically with the input/output pad and the anode connects with a ground terminal; and

an ESD protection circuit coupled to the input/output pad and the ground terminal, wherein the ESD protection circuit at least includes two output terminals that connect with the first gate and the second gate of the SOI-SCR device.

2. The ESD protection circuit of claim 1, wherein the SOI-SCR device is a N-type SOI-SCR device, and the first gate and the second gate are N-doped gates.

3. The ESD protection circuit of claim 2, wherein the ESD protection circuit further includes:

a second-type MOS transistor having a source terminal connected to the input/output pad and a substrate;

a first-type MOS transistor having a drain terminal connected to the drain terminal of the first second-type MOS transistor, a source terminal connected to the ground terminal and a substrate, and a gate terminal connected to the gate terminal of the first second-type MOS transistor, wherein the drain terminals of the first-type and second-type MOS transistors both connecting to the first gate and the second gate of the N-type SOI-SCR device;

a resistor having a first terminal connected to the input/output pad and a second terminal connected to the gate terminal of the first second-type MOS transistor; and

a capacitor having a first terminal connected to the gate terminal of the first second-type MOS transistor and a second terminal connected to the ground terminal.

4. The ESD protection circuit of claim 1, wherein the SOI-SCR device is a P-type SOI-SCR device, and the first gate and the second gate are P-doped gates.

5. An electrostatic discharge (ESD) protection circuit having a silicon-on-insulator (SOD) silicon controlled rectifier (SCR) device thereon for coupling with a first voltage source and a second voltage source, wherein the ESD protection circuit includes:

an SOI-SCR device having a cathode, an anode, a first gate and a second gate, wherein the cathode connects electrically with the first voltage source;

an ESD protection circuit that couples with the first voltage source and the second voltage source, wherein the ESD protection circuit at least includes two output terminals that connect with the first gate and the second gate of the SOI-SCR device; and

a diode series comprising a plurality of serially connected diodes, wherein a cathode of the diode series connects with the anode of the SOI-SCR device while the anode of the diode series connects with the second voltage source.

6. The ESD protection circuit of claim 5, wherein the SOI-SCR device is a N-type SOI-SCR device, and the first gate and the second gate are N-doped gates.

7. The ESD protection circuit of claim 5, wherein the SOI-SCR device is a P-type SOI-SCR device, and the first gate and the second gate are P-doped gates.

8. The ESD protection circuit of claim 7, wherein the circuit further includes:

a first second-type MOS transistor having a source terminal connected to the first voltage source, and a substrate connected to the source terminal;

a first first-type MOS transistor having a drain terminal connected to the drain terminal of the first second-type MOS transistor, a source terminal connected to the second voltage source, a gate terminal connected to the gate terminal of the second-type MOS transistor, a substrate connected to its source terminal;

a second second-type MOS transistor having a source terminal connected to the first voltage source, and a substrate connected to the source terminal;

a second first-type MOS transistor having a drain terminal connected to the drain terminal of the second second-type MOS transistor, a source terminal connected to the second voltage source, a gate terminal connected to the gate terminal of the second second-type MOS transistor and drains of the first second-type and first first-type MOS transistors, a substrate connected to its source terminal, wherein the drains of the second first-type and second second-type MOS transistors both connecting to the first and second gates of the P-type SOI-SCR device;

a resistor having a first terminal connected to the first voltage source and a second terminal connected to the gate terminal of the first second-type MOS transistor; and

a capacitor having a first terminal connected to the gate terminal of the first second-type MOS transistor and a second terminal connected to the second voltage source.