High density internal ball grid array integrated circuit package
First Claim
1. An integrated circuit package comprising:
- a multilayer substrate comprising a top layer having a top surface and a bottom layer having a bottom surface opposite said top surface, said top and said bottom layers having a plurality of overlapping peripheral openings, wherein said openings are larger in said top layer than in said bottom layer such that a portion of a top surface of said bottom layer is exposed;
a plurality of routing strips on said top surface of said bottom layer, wherein at least one of said routing strips is on said exposed portion of said top surface of said bottom layer;
a chip adhered to said bottom surface of said bottom layer of said substrate;
a plurality of electrical conductors physically attached to said chip and located such that each electrical conductor in said plurality of electrical conductors is aligned within a respective one of said plurality of peripheral openings in said substrate;
a plurality of pads disposed on said top surface of said top layer of said substrate generally centralized within said peripheral openings of said substrate; and
potting material filling said peripheral openings.
1 Assignment
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Accused Products
Abstract
An integrated circuit package (30) comprising a substrate (70) having peripheral openings (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70), a plurality of pads (100) centrally disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) adhered to the second surface (84) of the substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the openings (86) to adhere the chip (50) to the substrate (70) and surrounding the wire bonding (80), is disclosed.
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Citations
20 Claims
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1. An integrated circuit package comprising:
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a multilayer substrate comprising a top layer having a top surface and a bottom layer having a bottom surface opposite said top surface, said top and said bottom layers having a plurality of overlapping peripheral openings, wherein said openings are larger in said top layer than in said bottom layer such that a portion of a top surface of said bottom layer is exposed;
a plurality of routing strips on said top surface of said bottom layer, wherein at least one of said routing strips is on said exposed portion of said top surface of said bottom layer;
a chip adhered to said bottom surface of said bottom layer of said substrate;
a plurality of electrical conductors physically attached to said chip and located such that each electrical conductor in said plurality of electrical conductors is aligned within a respective one of said plurality of peripheral openings in said substrate;
a plurality of pads disposed on said top surface of said top layer of said substrate generally centralized within said peripheral openings of said substrate; and
potting material filling said peripheral openings. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit package comprising:
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a multilayer substrate comprising a top layer having a top surface and a bottom layer having a bottom surface opposite said top surface, said top and said bottom layers having a plurality of overlapping peripheral openings, wherein said openings are larger in said top layer than in said bottom layer such that a portion of a top surface of said bottom layer is exposed;
a plurality of routing strips on said top surface of said bottom layer, wherein at least one of said routing strips is on said exposed portion of said top surface of said bottom layer;
a plurality of pads disposed centrally on said top surface, at feast one of said pads being electrically connected with said at least one of said routing strips;
potting material filling said plurality of peripheral openings;
a chip having a plurality of bonding pads physically attached to the chip and located such that each bonding pad in said plurality of bonding pads is aligned within a respective one of said plurality of peripheral openings in said substrate; and
wire bonding electrically connecting said chip to said substrate between at least one of said bonding pads and said at least one of said routing strips on said exposed portion of said top surface of said bottom layer. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. An integrated circuit package comprising:
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a substrate having a plurality of peripheral openings, first and second surfaces and an outline;
a plurality of routing strips being integral with said substrate;
a plurality of pads centrally disposed on said first surface at least one of said pads being electrically connected with said routing strips;
a chip adhered to said second surface of said substrate, said chip having an outline that is substantially the same as said outline of said substrate and having a plurality of bonding pads physically attached to the chip and located such that each bonding pad in said plurality of bonding pads is aligned within a respective one of said plurality of peripheral openings in said substrate;
wire bonding electrically connecting said bonding pads to said routing strips;
vias connecting said routing strips to said pads;
potting material filling said peripheral openings and covering said wire bonding and said bonding pads; and
a plurality of solder balls centrally disposed on said pads disposed on said first surface of said substrate. - View Dependent Claims (17, 18, 19, 20)
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Specification