High density internal ball grid array integrated circuit package

• US 6,768,646 B1
• Filed: 07/14/1998
• Issued: 07/27/2004
• Est. Priority Date: 01/23/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ong, Pang Hup, Chen, Fung Leng, Yew, Chee Kiang
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): DINH, TUAN T
• Application Number:
  US09/115,444
• Time in Patent Office: 2,205 Days
• Field of Search: 361/748-750, 361/760-764, 361/767-770, 361/730, 361/803, 361/688, 361/792, 361/692, 361/735, 174/260-264, 174/250, 174/254, 174/52.1, 257/777-780, 257/734, 257/737, 257/738, 257/723, 257/724, 257/668
• US Class Current: 361/748
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/91 Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An integrated circuit package (30) comprising a substrate (70) having peripheral openings (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70), a plurality of pads (100) centrally disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) adhered to the second surface (84) of the substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the openings (86) to adhere the chip (50) to the substrate (70) and surrounding the wire bonding (80), is disclosed.

Claims

1. An integrated circuit package comprising:

a multilayer substrate comprising a top layer having a top surface and a bottom layer having a bottom surface opposite said top surface, said top and said bottom layers having a plurality of overlapping peripheral openings, wherein said openings are larger in said top layer than in said bottom layer such that a portion of a top surface of said bottom layer is exposed;

a plurality of routing strips on said top surface of said bottom layer, wherein at least one of said routing strips is on said exposed portion of said top surface of said bottom layer;

a chip adhered to said bottom surface of said bottom layer of said substrate;

a plurality of electrical conductors physically attached to said chip and located such that each electrical conductor in said plurality of electrical conductors is aligned within a respective one of said plurality of peripheral openings in said substrate;

a plurality of pads disposed on said top surface of said top layer of said substrate generally centralized within said peripheral openings of said substrate; and

potting material filling said peripheral openings.

2. The integrated circuit package as recited in claim 1 wherein at least one of said pads disposed on said top surface of said top layer of said substrate is electrically connected with said at least one of said routing strips.

3. The integrated circuit package as recited in claim 1 further comprising at least one solder ball disposed on one of said pads.

4. The integrated circuit package as recited in claim 1 further comprising a plurality of solder balls disposed on said pads.

5. The integrated circuit package as recited in claim 1 wherein said potting material adheres said chip to said substrate.

6. The integrated circuit package of claim 1 wherein each of the plurality of conductors comprises a bonding pad.

7. The integrated circuit package as recited in claim 2 wherein at least one of said pads disposed on said top surface of said top layer of said substrate is electrically connected with said at least one of said routing strips with a via through said top layer of said substrate.

8. An integrated circuit package comprising:

a multilayer substrate comprising a top layer having a top surface and a bottom layer having a bottom surface opposite said top surface, said top and said bottom layers having a plurality of overlapping peripheral openings, wherein said openings are larger in said top layer than in said bottom layer such that a portion of a top surface of said bottom layer is exposed;

a plurality of routing strips on said top surface of said bottom layer, wherein at least one of said routing strips is on said exposed portion of said top surface of said bottom layer;

a plurality of pads disposed centrally on said top surface, at feast one of said pads being electrically connected with said at least one of said routing strips;

potting material filling said plurality of peripheral openings;

a chip having a plurality of bonding pads physically attached to the chip and located such that each bonding pad in said plurality of bonding pads is aligned within a respective one of said plurality of peripheral openings in said substrate; and

wire bonding electrically connecting said chip to said substrate between at least one of said bonding pads and said at least one of said routing strips on said exposed portion of said top surface of said bottom layer.

9. The integrated circuit package as recited in claim 8 further comprising at least one solder ball disposed on one of said pads.

10. The integrated circuit package as recited in claim 8 further comprising a plurality of solder balls disposed on said pads.

11. The integrated circuit package as recited in claim 8 wherein said chip has a thickness between about 10 and 20 mils.

12. The integrated circuit package as recited in claim 8 wherein said substrate has a thickness of between about 8 and 28 mils.

13. The integrated circuit package as recited in claim 8 wherein said substrate has first and second layers and wherein said first layer has a thickness of about 12 mils and said second layer has a thickness of about 8 mils.

14. The integrated circuit package as recited in claim 8 wherein said at least one of said pads being electrically connected with said at least one of said routing strips is connected by a via through said top layer of said substrate.

15. The integrated circuit package as recited in claim 9 wherein said at least one solder ball is between about 8 and 20 mils in diameter.

16. An integrated circuit package comprising:

a substrate having a plurality of peripheral openings, first and second surfaces and an outline;

a plurality of routing strips being integral with said substrate;

a plurality of pads centrally disposed on said first surface at least one of said pads being electrically connected with said routing strips;

a chip adhered to said second surface of said substrate, said chip having an outline that is substantially the same as said outline of said substrate and having a plurality of bonding pads physically attached to the chip and located such that each bonding pad in said plurality of bonding pads is aligned within a respective one of said plurality of peripheral openings in said substrate;

wire bonding electrically connecting said bonding pads to said routing strips;

vias connecting said routing strips to said pads;

potting material filling said peripheral openings and covering said wire bonding and said bonding pads; and

a plurality of solder balls centrally disposed on said pads disposed on said first surface of said substrate.

17. The integrated circuit package as recited in claim 16 wherein said chip has a thickness between about 10 and 20 mils.

18. The integrated circuit package as recited in claim 16 wherein said substrate has a thickness of between about 8 and 28 mils.

19. The integrated circuit package as recited in claim 16 wherein said substrate has first and second layers and wherein said first layer has a thickness of about 12 mils and said second layer has a thickness of about 8 mils.

20. The integrated circuit package as recited in claim 19, wherein said peripheral openings in said second layer are larger than the peripheral openings in said first layer, such that a portion of a top surface of said first layer is exposed in each of said peripheral openings in said second layer.