Multiple-mode memory and method for forming same

• US 6,768,661 B2
• Filed: 06/27/2002
• Issued: 07/27/2004
• Est. Priority Date: 06/27/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Moore, Christopher S., Vyvoda, Michael A.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/184,578
• Publication Number:
  US 20040001348A1
• Time in Patent Office: 761 Days
• Field of Search: 365/51, 365/63, 365/195, 365/185.05, 365/185.33
• US Class Current: 365/51
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2216/26 Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability

Abstract

A multiple-mode memory includes a three-dimensional array of word lines, bit lines and memory cells. The memory cells are arranged in multiple vertically stacked layers. In some layers the memory cells are implemented as field-programmable write-once memory cells, and in other layers the memory cells are implemented as field-programmable re-writable memory cells. In this way, both re-writability and permanent data storage are provided in an inexpensive, single-chip solution. Additional types and numbers of types of memory cells can be used.

Claims

1. A multiple-mode memory comprising:

an integrated circuit substrate;

a plurality of word lines;

a plurality of bit lines crossing the word lines;

a plurality of memory cells, each memory cell coupled between a respective word line and a respective bit line, the word lines, bit lines and memory cells included in a single integrated circuit carried by the substrate;

the memory cells comprising a plurality of field-programmable write-once memory cells and a plurality of field-programmable re-writable memory cells.

2. The invention of claim 1 wherein each field-programmable write-once memory cell comprises a respective anti-fuse layer.

3. The invention of claim 2 wherein each field-programmable write-once memory cell additionally comprises a respective pair of oppositely-doped diode components.

4. The invention of claim 3 wherein each anti-fuse layer is interposed between the diode components of the respective memory cell.

5. The invention of claim 1 wherein each memory cell comprises at least two opposed side walls auto-aligned with at least two side edges of the respective adjacent bit line.

6. The invention of claim 1 wherein each memory cell comprises at least two opposed side walls auto-aligned with at least two side edges of the respective adjacent word line.

7. The invention of claim 1 wherein the word lines are stacked in multiple levels, wherein the bit lines are stacked in multiple levels, and wherein the memory cells are stacked in multiple levels.

8. The invention of claim 7 wherein the memory cell levels comprise levels j and k, wherein level j comprises a plurality of the field-programmable write-once memory cells and none of the field-programmable re-writable memory cells, and wherein level k comprises a plurality of the field-programmable re-writable memory cells and none of the field-programmable write-once memory cells.

9. The invention of claim 1 further comprising:

I/O circuitry carried by the substrate and coupled both with the field-programmable write-once memory cells and with the field-programmable re-writable memory cells via the respective word lines and bit lines.

10. The invention of claim 1, wherein the plurality of field-programmable re-writable memory cells comprises TFT-SONOS re-writeable memory cells.

11. A method for forming a multiple-mode memory, the method comprising:

(a) providing an integrated circuit substrate;

(b) forming a set of first levels of field-programmable write-once memory cells carried by and overlying the substrate; and

(c) forming a set of second levels of field-programmable re-writable memory cells carried by and overlying the substrate;

the first and second levels of memory cells vertically stacked on the substrate in a three-dimensional memory array.

12. The method of claim 11 wherein (b) comprises:

(b1) forming a respective anti-fuse layer in each field-programmable write-once memory cell.

13. The method of claim 12 wherein (b) further comprises:

(b2) forming a pair of oppositely-doped diode components in each field-programmable write-once memory cell.

14. The method of claim 13 wherein each anti-fuse layer is interposed between the diode components of the respective memory cell.

15. The method of claim 11 wherein (b) comprises:

(b1) patterning at least two opposed side walls of a plurality of the field-programmable write-once memory cells and two side edges of an adjacent word line with a single photolithographic operation.

16. The method of claim 11 wherein (b) comprises:

(b1) patterning at least two opposed side walls of a plurality of the field-programmable write-once memory cells and two side edges of an adjacent bit line with a single photolithographic operation.

17. The method of claim 11, wherein the field-programmable re-writable memory cells comprise TFT-SONOS re-writeable memory cells.

18. A multiple-mode memory comprising:

an integrated circuit substrate;

a plurality of word lines;

a plurality of bit lines crossing the word lines;

a plurality of memory cells, each memory cell coupled between a respective word line and a respective bit line, the word lines, bit lines and memory cells included in a single integrated circuit carried by the substrate;

the memory cells comprising a plurality of memory cells of a first type and a plurality of memory cells of a second type;

wherein the memory cells of the first type comprise field-programmable write-once memory cells, and wherein the memory cells of the second type comprise field-programmable re-writable memory cells.

19. The invention of claim 18, wherein the memory cells of the first type have a different write time than the memory cells of the second type.

20. The invention of claim 18, wherein the memory cells of the first type have a different read time than the memory cells of the second type.

21. The invention of claim 18, wherein the memory cells of one of the first type and the second type are programmed during manufacturing, and wherein the memory cells of the other of the first type and the second type are programmed in the field.

22. The invention of claim 21, wherein the memory cells of one of the first type and the second type store register settings, and wherein the memory cells of the other of the first type and the second type store data.

23. The invention of claim 18, wherein the memory cells of one of the first type and the second type store a different data type than the memory cells of the other of the first type and the second type.

24. The invention of claim 23, wherein the memory cells of one of the first type and the second type store a file system structure, and wherein the memory cells of the other of the first type and the second type store a digital media file.

25. The invention of claim 23, wherein the memory cells of one of the first type and the second type are assigned a different level of cache hierarchy than the memory cells of the other of the first type and the second type.

26. The invention of claim 18, wherein the memory cells further comprise a plurality of memory cells of a third type.

27. The invention of claim 18, wherein the word lines are stacked in multiple levels, wherein the bit lines are stacked in multiple levels, and wherein the memory cells are stacked in multiple levels.

28. The invention of claim 18 further comprising:

I/O circuitry carried by the substrate and coupled both with the plurality of memory cells of the first type and the plurality of memory cells of the second type via the respective word lines and bit lines.