Flexible SONET access and transmission system

• US 6,768,745 B1
• Filed: 03/31/1999
• Issued: 07/27/2004
• Est. Priority Date: 04/29/1998
• Status: Expired due to Fees

• Current Assignee: Summit Technology Systems LP
• Original Assignee: Zhone Technologies Incorporated (DZS, Inc.)
• Inventors: Gorshe, Steven Scott, Brooks, Robert Wesley
• Primary Examiner(s): NGUYEN, HANH N
• Application Number:
  US09/282,407
• Time in Patent Office: 1,945 Days
• Field of Search: 370/907, 370/375, 370/376, 370/539, 370/357-360, 370/362-364, 370/377-381, 370/384, 370/538, 370/541, 370/463, 370/401-403, 370/395, 370/438, 370/451, 370/502, 370/421, 370/378, 370/366, 370/432, 370/433, 370/434, 370/535, 370/422, 370/423, 398/58, 398/59, 398/60, 398/73
• US Class Current: 370/421
• CPC Class Codes: H04J 2203/0026 Physical details
• CPC Class Codes: H04J 2203/0041 Star, e.g. cross-connect, concentrator, subscriber group equipment, remote electronics
• CPC Class Codes: H04J 2203/0042 Ring
• CPC Class Codes: H04J 2203/006 Fault tolerance and recovery
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04J 3/08 Intermediate station arrangements, e.g. for branching, for tapping-off
• CPC Class Codes: H04J 3/1617 carrying packets or ATM cells
• CPC Class Codes: Y10S 370/907 Synchronous optical network, SONET

Abstract

A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween. The interface having: a common bus of predetermined bit width for interfacing the HSU unit with each of the LSU units to enable transmission of signals from each of the LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs; a first partition bus of the predetermined bit width for interfacing the HSU to a predetermined number of the LSUs, the first partition bus being partitioned into a first bus for interfacing the HSU to a first subset of the LSUs and a second bus for interfacing the HSU to a second subset of the LSUs; and a second partition bus of the predetermined bit width for interfacing the HSU to a predetermined number of the LSU units.

Claims

1. A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:

a common bus of predetermined bit width for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;

a first partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSUs, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs; and

a second partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSU units, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs; and

an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI) connected to the at least one HSU of a shelf unit for exchange data between the shelf unit and the expansion shelf;

wherein the first, second, third, and fourth buses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network;

wherein the at least one HSU, at least two LSUs, and common, first and second partition buses, are contained in the shelf unit;

wherein the shelf unit further comprises a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;

wherein the data transmitted from the expansion shelf has the same frame alignment as the data transmitted from the shelf unit relative to the at least one HSU for eliminating the need for frame alignment buffering on the at least one HSU.

2. The SONET network interface of claim 1, wherein the bandwidth and format of the common, first partition, and second partition buses is STS-1.

3. The SONET network interface of claim 1, wherein each of the common, first partition, and second partition buses contains four parallel data lines.

4. The SONET network interface of claim 3, wherein each of the common, first partition, and second partition buses further contains a byte status line for indicating the contents of the four parallel data lines.

5. The SONET network interface of claim 3, wherein data is placed onto the four parallel data lines of each of the common, first partition, and second partition buses in a high/low byte format.

6. The SONET network interface of claim 3, wherein data is placed onto the four parallel data lines of each of the common, first partition, and second partition buses in an odd/even byte format.

7. The SONET network interface of claim 1, wherein each of the LSUs are selected from a group consisting of voice frequency channel units (CHUs), wideband units, broadband units, and common processing units.

8. The SONET network interface of claim 7, further comprising a backplane connector for connecting the LSUs to their required signals, the backplane connector having a first subset of connections for connecting one of the CHUs, wideband units, broadband units, or common processing units to their required signals.

9. The SONET network interface of claim 8, wherein the first subset of connections of the backplane connector connects the CHUs to their required signals.

10. The SONET network interface of claim 1, wherein the interface comprises first and second HSUs, each HSU being interconnected to the at least two LSUs via the common, first partition, and second partition buses.

11. The SONET network interface of claim 1, further comprising a backplane local area network for allowing exchange of packet data within the signals with data processing LSUs.

12. The SONET network interface of claim 11, wherein the backplane local area network provides Internet services.

13. The SONET network interface of claim 1, wherein the bandwidth and format of the common, first partition, and second partition buses is STS-1 and wherein the first subset of LSU'"'"'s has a capacity of OC-3.

14. The SONET network interface of claim 1, wherein the bandwidth and format of the common, first partition, and second partition buses is STS-1 and wherein line, section, STS path, and VT path termination functions are performed on the at least one HSU.

15. The SONET network interface of claim 1, wherein the bandwidth and format of the common, first partition, and second partition buses is STS-1 and at least one of the at least two LSUs are voice frequency channel units (CHUs), whereby the at least one HSU serves as a common location where DS1 and VT1.5 overhead information is added to the transmitted signal.

16. The SONET network interface of claim 15, wherein the DS1 is also terminated in the at least one HSU.

17. The SONET network interface of claim 1, wherein at least one of the LSUs generate virtual tributaries for generating all of the transmit overhead for those virtual tributaries and wherein the at least one LSU that generate STS-1s generate all of the transmit overhead for those STS-1s.

18. The SONET network interface of claim 1, wherein the expansion shelf further has at least one power supply unit for powering the units contained on the expansion shelf.

19. The SONET network interface of claim 1, wherein the frame alignment between the main shelf and the expansion shelf allows hairpinned exchanged of PCM data between LSUs in the main and expansion shelves.

20. A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:

a common bus of predetermined bit width for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;

a first partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSUs, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs; and

a second partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSU units, the second partition bus being partitioned into a third bus for interlacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs; and

an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI) connected to the at least one HSU of a shelf unit for exchanging data between the shelf unit and the expansion shelf;

wherein the first, second, third, and fourth buses of respective first and second partition buses have a bit width less tar the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network;

wherein the at least one HSU, at least two LSUs, and common, first and second partition buses, are contained in the shelf unit;

wherein the shelf unit further comprises a system control processor unit (SCU) for controlling the processes of the units contained in the shelf at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;

wherein a local area network exists between the shelf unit and the expansion shelf such that LSUs in the expansion shelf can communicate control, alarm or signaling information directly with common-processing HSUs or LSUs in the shelf unit.

21. The SONET network interface of claim 20, wherein the interface comprises twenty four LSUs, six of which comprise the first subset and the remaining comprising the second subset.

22. The SONET network interface of claim 20, wherein the interface comprises:

two HSUs, each HSU being interconnected to the at least two LSUs via the common, first partition, and second partition buses; and

twenty four LSUs, six of which comprise the first subset and the remaining comprising the second subset.

23. The SONET network interface of claim 20, wherein the first and second, or third and fourth buses operate at different bus rates.

24. The SONET network interface of claim 23, wherein the bandwidth and format of the first partition and second partition buses is STS-3.

25. The SONET network interface of claim 20, wherein the first and second or third and fourth buses operate at the same bus rates.

26. The SONET network interface of claim 20, wherein a receive direction of at least one of the common, first, second, third, and fourth buses operates at a higher rate than that used by a transmit direction of these buses.

27. A SONET network interface of for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:

a common bus of predetermined bit width for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;

a first partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSUs, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs; and

a second partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSU units, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs; and

an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI) connected to the at least one HSU of a shelf unit for exchanging data between the shelf unit and the expansion shelf;

wherein the first, second, third, and fourth buses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network;

wherein the at least one HSU, at least two LSUs, and common, first and second partition buses, are contained in the shelf unit;

wherein the shelf unit further comprises a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;

wherein some of the at least two LSU'"'"'s which perform a common processing function on the first and third buses at a STS-3 rate process all of the data from all LSUs connected to the second and fourth buses and the at least one expansion LSU in the expansion shelf, and wherein in a receive direction, STS-3 data is sent over the first bus from the at least one HSU to the common processing LSU'"'"'s, processed by the common processing LSU'"'"'S, and sent back over the first bus from the common processing LSU'"'"'s to the at least one HSU, processed received data is subsequently sent from the at least one HSU over the common bus, second bus, fourth bus, and expansion shelf interface to the at least one LSUs, wherein the transmit data from the at least one LSUs that is sent to the at least one HSU over the common bus, second bus, fourth bus, or expansion interface unit is sent by the at least one HSU over the third bus at STS-3 rate to the at least one common processing LSU, the at least one common processing LSU processing the transmit data and sends it back to the at least one HSU for subsequent transmission.

28. A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals between the HSU and LSUs, the method comprising:

interfacing the at least one HSU unit with each of the at least two LSU units by means of a common bus of predetermined bit width to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;

interfacing the at least one HSU to a predetermined number of the at least two LSUs by means of a first partition bus of the predetermined bit width, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs;

interfacing the at least one HSU to a predetermined number of the at least two LSU units using a second partition bus of the predetermined bit width, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;

containing the at least one HSU, at least two LSUs, and the common, first and second partition buses, in a shelf unit;

providing the shelf unit with a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;

providing an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI);

connecting the at least one HSU of the shelf unit for exchanging data between the shelf unit and the expansion shelf, and

providing the expansion shelf with at least one power supply unit for powering the units contained on the expansion shelf; and

aligning the data transmitted from the expansion shelf to the data transmitted from the shelf unit such that the data transmitted from the expansion shelf has the same frame alignment as the data transmitted from the shelf unit relative to the at least one HSU for eliminating the need for frame alignment buffering on the at least one HSU,

whereby the first, second, third and fourth busses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network.

29. The method of claim 28, further comprising the step of providing an STS-1 bandwidth and format for the common, first partition, and second partition buses.

30. The method of claim 28, further comprising the step of providing an STS-3 bandwidth and format for the first partition and second partition buses.

31. The method of claim 28, further comprising the step of partitioning each of the common, first partition, and second partition buses to contain four parallel data lines.

32. The method of claim 31, further comprising the step of placing data onto the four parallel data lines of each of the common, first partition, and second partition buses in a high/low byte format.

33. The method of claim 31, further comprising the step of placing data onto the four parallel data lines of each of the common, first partition, and second partition buses in an odd/even byte format.

34. The method of claim 28, wherein the interface comprises first and second HSUs, and further comprising the step of interconnecting each HSU to the at least two LSUs via the common, first partition, and second partition buses.

35. The method of claim 28, further comprising the step of providing a backplane local area network for allowing exchange of packet data within the signals with data processing LSUs.

36. The method of claim 35, wherein the backplane local area network provides Internet services.

37. The method of claim 28, wherein the bandwidth and format of the common, first partition, and second partition buses is STS-1 and further comprising the step of performing line, section, STS path, and VT path the termination functions on the at least one HSU.

38. The method of claim 28, wherein the bandwidth and format of the common, first partition, and second partition buses is STS-1 and at least one of the at least two LSUs are voice frequency channel units (CHUs), further comprising the step of adding DS1 and VT1.5 overhead information to the transmitted signal such that the at least one HSU serves as a common location.

39. The method of claim 28, wherein at least one of the LSUs generate virtual tributaries for generating all of the transit overhead for those virtual tributaries and wherein the at least one LSU that generate STS-1s generate all of the transmit overhead for those STS-1s.

40. The method of claim 28, wherein the frame alignment between the main shelf and the expansion shelf allows hairpinned exchanged of PCM data between LSUs in the and expansion shelves.

41. A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals between the HSU and LSUs, the method comprising:

interfacing the at least one HSU unit with each of the at least two LSU units by means of a common bus of predetermined bit width to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;

interfacing the at least one HSU to a predetermined number of the at least two LSUs by means of a first partition bus of the predetermined bit width, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs;

interfacing the at least one HSU to a predetermined number of the at least two LSU units using a second partition bus of the predetermined bit width, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;

containing the at least one HSU, at least two LSUs, and the common, first and second partition buses, in a shelf unit;

providing the shelf unit with a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;

providing an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI);

connecting the at leas one HSU of the shelf unit for exchanging data between the shelf unit and the expansion shelf; and

a local area network between the shelf unit and the expansion shelf such that LSUs in the expansion shelf can communicate control, alarm, or signaling information directly with common-processing HSUs or LSUs in the shelf unit,

whereby the first, second, third, and fourth buses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network.

42. The method of claim 41, further comprising the step of operating the first and second or third and fourth buses at different bus rates.

44. The method of claim 41, wherein the bandwidth and format of the first partition and second partition buses is STS-3.

45. The method of claim 44, further comprising the step of operating the first and second or third and fourth buses at the same bus rates.

43. The method of claim further comprising the step of terminating the DS1 in the at least one HSU.

46. A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals between the HSU and LSUs, the method comprising:

interfacing the at least one HSU unit with each of the at least two LSU units by means of a common bus of predetermined bit width to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;

interfacing the at least one HSU to a predetermined number of the at least two LSUs by means of a first partition bus of the predetermined bit width, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs;

interfacing the at least one HSU to a predetermined number of the at least two LSU units using a second partition bus of the predetermined bit width, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;

containing the at least one HSU, at least two LSUs, and the common, first and second partition buses, in a shelf unit;

providing the shelf unit with a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;

providing an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI);

connecting the at least one HSU of the shelf unit for exchanging data between the shelf unit and the expansion shelf; and

providing the expansion shelf with at least one power supply unit for powering the units contained on the expansion shelf; and

whereby the first second, third, and fourth busses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network;

wherein some of the at least two LSUs which perform a common processing function on the first and third buses at a STS-3 rate process all of the data from all LSUs connected to the second and fourth buses and the at least one expansion LSU in the expansion shelf, and wherein in a receive direction STS-3 data is sent over the first bus from the at least one HSU to the common processing LSU'"'"'s, processed by the common processing LSU'"'"'s, and sent back over the first bus from the common processing LSU'"'"'s to the at least one HSU, processed received data is subsequently sent from the at least one HSU over the common bus, second bus, fourth bus, and expansion shelf interface to the at least one LSUs, wherein the transmit data from the at least one LSUs that is sent to the at least one HSU over the common bus, second bus, fourth bus, or expansion interface unit is sent by the at least one HSU over the third bus at STS-3 rate to the at least one common processing LSU, the at least one common processing LSU processing the transmit data and sends it back to the at least one HSU for subsequent transmission.