Method and apparatus for providing bimodal voltage references for differential signaling

• US 6,769,041 B2
• Filed: 04/01/2002
• Issued: 07/27/2004
• Est. Priority Date: 08/30/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dahlen, Eric J., Cross, Leonard W.
• Primary Examiner(s): Elamin, A.
• Application Number:
  US10/114,157
• Publication Number:
  US 20020108067A1
• Time in Patent Office: 848 Days
• Field of Search: 710/62, 365/149, 365/63, 365/68
• US Class Current: 710/62
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

According to an embodiment of the invention, systems, apparatus and methods are disclosed for providing bimodal voltage references for use in differential signaling between components or devices. According to an embodiment, a switchable power supply is used to produce at least one of two or more supply voltages based on the value of a selection signal received by the switchable power supply. This selection signal is also used by at least one of the elements to switch between a reference voltage produced by another device and a reference voltage derived from the supply voltage. In certain embodiments, the reference voltage derived from the power supply and the selection via a multiplexing circuit is contained within one of the devices (e.g., a chip), which provides certain design and cost advantages.

Claims

1. A system comprising:

a first component requiring a first reference voltage;

a second component requiring a second reference voltage;

a power source to produce a supply voltage;

a first voltage reducer electrically coupled to the power source, the first voltage reducer to produce a third reference voltage using the supply voltage;

a multiplexor electrically coupled to the first voltage reducer to produce the first reference voltage by selecting between at least the third reference voltage and a fourth reference voltage; and

a second voltage reducer electrically coupled to the power source and to the second component, the second voltage reducer to produce the second reference voltage using the supply voltage.

2. The system of claim 1, wherein the power source is selectively operable to produce at least one of a first supply voltage and a second supply voltage, and the multiplexor is operable to,select the third reference voltage when the power supply produces the first supply voltage.

3. The system of claim 2, further comprising a selection signal electrically coupled to a selection input of the power source and a selection input of the multiplexor.

4. The system of claim 1, wherein the power source is selectively operable to produce at least one of a first supply voltage and a second supply voltage, and the multiplexor is operable to select the fourth reference voltage when the power supply produces the second supply voltage.

5. A system comprising:

a power source to produce a supply voltage;

a first component requiring a first reference voltage, the first component including;

a first voltage reducer electrically coupled to the power source, the first voltage reducer to produce a third reference voltage using the supply voltage; and

a multiplexor electrically coupled to the first voltage reducer to produce the first reference voltage by selecting between at least the third reference voltage and a fourth reference voltage;

a second component requiring a second reference voltage; and

a second voltage reducer not located on the first component of the system and electrically coupled to the power source and the second component, the second voltage reducer to produce the second reference voltage using the supply voltage.

6. The system of claim 5, wherein the power source is selectively operable to produce at least one of a first supply voltage and a second supply voltage, and the multiplexor is operable to select the third reference voltage when the power supply produces the first supply voltage.

7. The system of claim 6, further comprising a selection signal electrically coupled to a selection input of the power source and a selection input of the multiplexor.

8. The system of claim 5, wherein the power source is operable to produce at least one of a first supply voltage and a second supply voltage, and the multiplexor is operable to select the fourth reference voltage when the power supply produces the second supply voltage.

9. The system of claim 5, wherein the first voltage reducer includes a voltage divider circuit.

10. The system of claim 5, wherein the first component is a chip and the second component is a slot for receiving the chip.

11. The system of claim 5, wherein the second component is an Accelerated Graphics Port (AGP) slot receiving the first component.

12. A chip requiring a first reference voltage, the chip comprising:

a first voltage reducer electrically coupled to receive a supply voltage, the first voltage reducer to produce a second reference voltage using the supply voltage; and

a multiplexor electrically coupled to the first voltage reducer and to receive a third reference voltage, the multiplexor operable to produce the first reference voltage by selecting between at least the second reference voltage and the third reference voltage.

13. The chip of claim 12, further electrically coupled to receive a selection signal, the selection signal electrically coupled to a selection input of the multiplexor.

14. The chip of claim 13, wherein the chip is an Accelerated Graphics Port compliant component.

15. A method performed by a chip for generating a first reference voltage, the method comprising:

receiving a second reference voltage;

receiving a third reference voltage;

reducing the third reference voltage;

receiving a selection signal; and

selecting as the first reference voltage, the second reference voltage or the reduced third reference voltage based on the received selection signal.

16. The method of claim 15, wherein reducing the third reference voltage includes a voltage divider circuit reducing the third voltage.

17. The method of claim 15, wherein the chip is an Accelerated Graphics Port compliant component.