Resetting a processor in an isolated execution environment

• US 6,769,058 B1
• Filed: 12/29/2000
• Issued: 07/27/2004
• Est. Priority Date: 03/31/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Reneris, Ken, Thakkar, Shreekant S., Neiger, Gilbert, Ellison, Carl M., Mittal, Millind, Lin, Derrick C., McKeen, Francis X., Sutton, James A., Herbert, Howard C., Golliver, Roger A.
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US09/751,586
• Time in Patent Office: 1,306 Days
• Field of Search: 713/1, 713/2, 713/100
• US Class Current: 713/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2009/45587 Isolation or security of virtual machine instances
• CPC Class Codes: G06F 21/53 by executing in a restricted environment, e.g. sandbox or secure virtual machine
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

A method, apparatus, and system for invoking a reset process in response to a logical processor being individually reset is disclosed. When a last logical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory is reset, it is reset without clearing a cleanup flag. Subsequently, an initializing physical processor invokes an initialization process that determines that the cleanup flag is set. The initialization process invokes the execution of a processor nub loader, and if the cleanup flag is set, the processor nub loader scrubs the isolated area of memory and invokes a controlled close for the initializing physical processor which clears the cleanup flag. The initializing physical processor then re-performs the initialization process. Upon the second iteration of the initialization process, with the cleanup flag not set, a new clean isolated area of memory is created for the initializing physical processor.

Claims

1. A method comprising:

invoking a reset process in response to a logical processor being individually reset, the reset logical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory;

determining whether the reset logical processor is a last logical processor of a physical processor and a last logical processor of the platform to be reset and if so,

invoking an initialization process for an initializing physical processor;

determining whether a cleanup flag is set; and

if the cleanup flag is set,

scrubbing the isolated area of memory.

2. The method of claim 1 wherein the initialization process for the initializing physical processor in which the cleanup flag is set further comprises clearing the cleanup flag and creating a new isolated area of memory for use by the initializing physical processor.

3. The method of claim 1 wherein if the cleanup flag is not set during the initialization process for the initializing physical processor a new isolated area of memory is created.

4. The method of claim 1 wherein the initializing physical processor utilizes the isolated area of memory associated with the reset logical processor.

5. The method of claim 1 wherein the initializing physical processor is a first physical processor to enroll in the initialization process including a first logical processor to enroll in the initialization process.

6. The method of claim 1 wherein the initializing physical processor communicates with an input/output controller hub (ICH), the ICH having isolated range values which correspond to the isolated area of memory.

7. The method of claim 1 wherein the initialization process for the initializing physical processor in which the cleanup flag is set further comprises:

reading an isolated range value from an input/output controller hub (ICH) corresponding to the isolated area of memory previously associated with the reset logical processor;

setting an isolated range value of the initializing physical processor to the isolated range value of the ICH; and

copying a processor nub loader into the isolated area of memory.

8. The method of claim 7 wherein the processor nub loader scrubs the isolated area of memory.

9. The method of claim 7 wherein the initializing physical processor undergoes a controlled close clearing the cleanup flag.

10. The method of claim 9 wherein the initialization process further comprises creating a new isolated area of memory for the initializing physical processor.

11. The method of claim 10 wherein creating the new isolated area of memory for the initializing physical processor comprises:

setting a new isolated range value for the initializing physical processor;

setting a new isolated range value in the ICH;

copying the processor nub loader into the new isolated area of memory; and

executing the processor nub loader.

12. The method of claim 11 wherein the initialization process further comprises initializing the new isolated area of memory for the platform.

13. The method of claim 11 wherein the initialization process further comprises setting the clean up flag.

14. An apparatus comprising:

a physical processor to invoke a reset process in response to a logical processor being individually reset, the reset logical processor and the physical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory, the physical processor to determine whether the reset logical processor is a last logical processor of the physical processor and a last logical processor of the platform to be reset; and

an initializing physical processor to invoke an initialization process if the physical processor determined that the reset logical processor was a last logical processor of the physical processor and a last logical processor of the platform to be reset, the initialization process to determine whether a cleanup flag is set; and

if the cleanup flag is set,

the initialization process invokes a processor nub loader to scrub the isolated area of memory.

15. The apparatus of claim 14 wherein if the cleanup flag is set the initialization process clears the cleanup flag and creates a new isolated area of memory for use by the initializing physical processor.

16. The apparatus of claim 14 wherein if the cleanup flag is not set the initialization process creates a new isolated area of memory.

17. The apparatus of claim 14 wherein the initializing physical processor utilizes the isolated area of memory associated with the reset logical processor.

18. The apparatus of claim 14 wherein the initializing physical processor is a first physical processor to enroll in the initialization process including a first logical processor to enroll in the initialization process.

19. The apparatus of claim 14 wherein the initializing physical processor communicates with an input/output controller hub (ICH), the ICH having isolated range values which correspond to the isolated area of memory.

20. The apparatus of claim 14 wherein if the cleanup flag is set the initialization process:

reads an isolated range value from an input/output controller hub (ICH) corresponding to the isolated area of memory previously associated with the reset logical processor;

sets an isolated range value of the initializing physical processor to the isolated range value of the ICH; and

copies a processor nub loader into the isolated area of memory.

21. The apparatus of claim 20 wherein the processor nub loader scrubs the isolated area of memory.

22. The apparatus of claim 20 wherein the initializing physical processor performs a controlled close clearing the cleanup flag.

23. The apparatus of claim 22 wherein the initialization process creates a new isolated area of memory for the initializing physical processor.

24. The apparatus of claim 23 wherein the initialization process creates the new isolated area of memory by:

setting a new isolated range value within the initializing physical processor;

setting a new isolated range value in the ICH;

copying the processor nub loader into the new isolated area of memory; and

executing the processor nub loader.

25. The apparatus of claim 24 wherein the new isolated area of memory is initialized for the platform.

26. The apparatus of claim 24 wherein the clean up flag is set.

27. A computer program product comprising:

a machine readable medium having computer code stored therein, the computer program product comprising;

computer readable program code for invoking a reset process in response to a logical processor being individually reset, the reset logical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory;

computer readable program code for determining whether the reset logical processor is a last logical processor of the platform to be reset and if so,

computer readable program code for invoking an initialization process for an initializing physical processor;

computer readable program code for determining whether a cleanup flag is set; and

if the cleanup flag is set,

scrubbing the isolated area of memory.

28. The computer program product of claim 27 wherein the computer readable program code for performing the initialization process for the initializing physical processor, when the cleanup flag is set, further comprises:

computer readable program code for clearing the cleanup flag; and

computer readable program code for creating a new isolated area of memory for use by the initializing physical processor.

29. The computer program product of claim 27 wherein the computer readable program code for performing the initialization process for the initializing physical processor, when the cleanup flag is not set, further comprises computer readable program code for creating a new isolated area of memory.

30. The computer program product of claim 27 further comprising computer readable program code for allowing the initializing physical processor to utilize the isolated area of memory associated with the reset logical processor.

31. The computer program product of claim 27 wherein the initializing physical processor is a first physical processor to enroll in the initialization process including a first logical processor to enroll in the initialization process.

32. The computer program product of claim 27 further comprising computer readable program code for allowing the initializing physical processor to communicate with an input/output controller hub (ICH), the ICH having isolated range values which correspond to the isolated area of memory.

33. The computer program product of claim 27 wherein the computer readable program code for performing the initialization process for the initializing physical processor, when the cleanup flag is set, further comprises:

computer readable program code for reading an isolated range value from an input/output controller hub (ICH) corresponding to the isolated area of memory previously associated with the reset logical processor;

computer readable program code for setting an isolated range value of the initializing physical processor to the isolated range value of the ICH; and

computer readable program code for copying a processor nub loader into the isolated area of memory.

34. The computer program product of claim 33 further comprising computer readable program code for allowing the processor nub loader to scrub the isolated area of memory.

35. The computer program product of claim 33 further comprising computer readable program code for performing a controlled close upon the initializing physical processor and clearing the cleanup flag.

36. The computer program product of claim 35 wherein the computer readable program code for initializing the initializing physical processor further comprises computer readable program code for creating a new isolated area of memory for the initializing physical processor.

37. The computer program product of claim 36 wherein the computer readable program code for creating the new isolated area of memory for the initializing physical processor further comprises:

computer readable program code for setting a new isolated range value for the initializing physical processor;

computer readable program code for setting a new isolated range value in the ICH;

computer readable program code for copying the processor nub loader into the new isolated area of memory; and

computer readable program code for executing the processor nub loader.

38. The computer program product of claim 37 further comprising computer readable program code for initializing the new isolated area of memory for the platform.

39. The computer program product of claim 37 further comprising computer readable program code for setting the clean up flag.

40. A system comprising:

a chipset;

a memory coupled to the chipset having an isolated area of memory;

a physical processor coupled to the chipset and the memory operating in a platform, the physical processor to invoke a reset process in response to a logical processor being individually reset, the reset logical processor and the physical processor operating within the platform in an isolated execution mode and associated with an isolated area of memory, the physical processor to determine whether the reset logical processor is a last logical processor of the physical processor and a last logical processor of the platform to be reset; and

an initializing physical processor to invokes an initialization process if the physical processor determined that the reset logical processor was a last logical processor of the physical processor and a last logical processor of the platform to be reset, the initialization process to determine whether a cleanup flag is set; and

if the cleanup flag is set,

the initialization process invokes a processor nub loader to scrub the isolated area of memory.

41. The system of claim 40 wherein if the cleanup flag is set the initialization process clears the cleanup flag and creates a new isolated area of memory for use by the initializing physical processor.

42. The system of claim 40 wherein if the cleanup flag is not set the initialization process creates a new isolated area of memory.

43. The system of claim 40 wherein the initializing physical processor utilizes the isolated area of memory associated with the reset logical processor.

44. The system of claim 40 wherein the initializing physical processor is a first physical processor to enroll in the initialization process including a first logical processor to enroll in the initialization process.