Scan circuit low power adapter with counter

• US 6,769,080 B2
• Filed: 03/09/2001
• Issued: 07/27/2004
• Est. Priority Date: 03/09/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US09/803,599
• Publication Number:
  US 20010047498A1
• Time in Patent Office: 1,236 Days
• Field of Search: 714/724, 714/726, 714/729, 714/733, 714/741
• US Class Current: 714/729
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318575 Power distribution; Power saving
• CPC Class Codes: G01R 31/318577 AC testing, e.g. current testing, burn-in

Abstract

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Claims

1. A scan circuit comprising:

A. a functional circuit formed on the semiconductor substrate of an integrated circuit, the functional circuit including logic circuits to be tested;

B. a scan path circuit formed of serially connected scan cells, the scan path circuit having leads connected to the logic circuits to carry stimulus signals to the logic circuits and to receive response signals from the logic circuits, the scan path circuit having a serial data input lead and a serial data output lead, the scan path circuit having control input leads for receiving control signals to control operation of the scan path circuit, the scan path circuit being organized in selectable, separate scan path parts, each scan path part having a serial input connected to the serial data input lead, a serial output lead selectively coupled to the serial data output lead and a separate set of control input leads;

C. a tester having a tester data output lead connected to the serial data input lead, a tester data input lead connected to the serial data output lead and control output leads coupled to the control input leads for controlling the operation of the scan path circuit; and

D. adaptor circuits coupling the control output leads of the tester to the separate sets of control input leads of the scan path circuit, the adaptor circuits including input leads receiving one set of control signals from the tester and including a set of output leads providing control signals for each scan path part, the adaptor circuits including a state machine controlling the production of the separate sets of control signals for operating the respective separate scan path parts, and the adaptor circuits including counter circuits connected to the state machine.

2. The circuit of claim 1 in which the state machine has counter control outputs and at least one count input, and the counter has control inputs connected to the counter control outputs and has at least one count output connected to the count input.

3. The circuit of claim 2 in which the scan path parts have equal numbers of scan cells and there is only one count input and one count output.

4. The circuit of claim 2 in which the scan paths have unequal numbers of scan cells and there are plural count outputs.

5. The circuit of claim 2 in which the state machine has a scan clock input, a scan enable input, an enable clock output for each scan path part, and an enable buffer output for each scan path part, the adaptor circuits including a gate for each scan path part, each gate having a first input connected to an enable clock output from the state machine and the scan clock input.