Method of physical design for integrated circuit

• US 6,769,098 B2
• Filed: 02/27/2001
• Issued: 07/27/2004
• Est. Priority Date: 02/29/2000
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Fukui, Masahiro, Tanaka, Masakazu, Tsukiyama, Shuji
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lin, Sun James
• Application Number:
  US09/793,564
• Publication Number:
  US 20010018758A1
• Time in Patent Office: 1,246 Days
• Field of Search: 716/1-19
• US Class Current: 716/106
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A physical design method optimizes the performance of an integrated circuit much more efficiently. After an initial layout is obtained for an integrated circuit, a set of process steps, including evaluating the overall performance of the integrated circuit, selecting a candidate cell and changing the performance of the cell, is carried out a number of times. In the step of selecting a candidate cell, a cell, which should have its performance changed, is selected from multiple cells included in the integrated circuit based on the performance evaluation result obtained. Then, by reference to a library, a characteristic representing the performance of the candidate cell is determined in accordance with an external condition imposed thereon.

Claims

1. A method of physical design for an integrated circuit made up of multiple cells, the method comprising the steps of:

a) evaluating the overall performance of the integrated circuit;

b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a); and

c) changing the performance of the candidate cell selected in the step b),

wherein in the step c), characteristic representing the performance of the candidate cell is determined in view of a specified external condition imposed on the candidate cell.

2. The method of claim 1, wherein in the step c), the performance of the cell is changed by reference to a library, on which information about the respective cells is stored and on which two or more mutually different performance characteristics, associated with a single external condition, are stored for at least one of the cells, and wherein if two or more mutually different performance characteristics, associated with the external condition imposed on the candidate cell, are stored on the library, one of these performance characteristics is selected.

3. The method of claim 1, wherein the external condition imposed on the candidate cell includes at least one of output load capacitance, input drive and input waveform.

4. The method of claim 1, wherein parameters representing the performance characteristic of the candidate cell include at least one parameter selected from the group consisting of delay, area, power dissipation, output drive and input load capacitance.

5. The method of claim 1, further comprising the step of:

a′

) determining relative positions of the cells and wires interconnecting the cells together in the integrated circuit,

wherein the steps a), b) and c) are performed repeatedly, and wherein no matter how many times the steps a) through c) are performed, the same relative positions of the cells and wires, determined in the step a′

), are maintained.

6. The method of claim 1, wherein the steps a), b) and c) are performed repeatedly, and wherein each aid cell should have a minimum area initially, and wherein in the step c), the performance of the candidate cell is changed by allowing the candidate cell to just increase its area.

7. A method of physical design for an integrated circuit made up of multiple cells, the method comprising the steps of:

preparing multiple evaluating approaches;

a) evaluating the overall performance of the integrated circuit;

b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a); and

c) changing the performance of the candidate cell selected in the step b),

wherein the steps a), b) and c) are performed repeatedly, and

wherein in the step a), one of the multiple evaluating approaches prepared is selected on a predetermined condition and the performances of the cells, included in the integrated circuit, are evaluate by the approach selected.

8. The method of claim 7, wherein according to one of the approaches, the size of transistors, which make up each said cell, is optimized with the area and performance of the cell taken into account, and then the performance of the cell, made up of the transistors of the optimized size, is evaluated.

9. The method of claim 7, wherein according to one of the approaches, the performance of at least one of the cells is evaluated by reference to a library, on which information about the respective cells is stored and on which two or more mutually different performance characteristics are stored for the cell, and by interpolating and approximating the two or more performance characteristics.

10. The method of claim 7, wherein the predetermined condition is presented considering at least priority levels of a specified length of a design process and target performance of the intergrated circuit.

11. The method of claim 7, wherein the predetermined condition is presented considering at least the number of times the steps a) through c) should be performed repeatedly.

12. The method of claim 7, wherein in the step a), the performance of each said cell is evaluated by reference to a library on which various performance characteristics, associated with respective external conditions, are stored for at least one of the cells, and wherein the predetermined condition is presented considering at least difference between an external condition currently imposed on the cell and the external condition stored on the library for the same cell.

13. The method of claim 7, wherein in the step a), the performance of each said cell is evaluated by reference to a library on which size information is stored as one of the performance characteristic, and wherein the predetermined condition is presented considering at least difference between information about the current size of the cell and the size information stored on the library for the same cell.

14. The method of claim 7, wherein in the step a), the performance of each said cell is evaluated by reference to a library on which the performance characteristics of the respective cells are stored, and wherein an alternative performance characteristic, which has been obtained for the cell as a result of the performance evaluation, is newly registered with the library.

15. The method of claim 7, further comprising the step of:

a′

) determining relative positions of the cells and wires interconnecting the cells together in the integrated circuit,

wherein no matter how many times the steps a) through c) are performed, the same relative positions of the cells and wires, determined in the step a′

), are maintained.

16. The method of claim 7, wherein each said cell should have a minimum area initially, and wherein in the step c), the performance of the candidate cell is changed by allowing the candidate cell to just increase its area.

17. A method of physical design for an integrated circuit made up of multiple cells, each cell includes a plurality of elements and performs a logic function, the method comprising the steps of:

a) determining relative positions of the cells and wires interconnecting the cells together in the integrated circuit;

b) evaluating a performance of the integrated circuit;

c) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step b); and

d) changing the performance of the candidate cell selected in the step c),

wherein the steps b), c) and d) are performed repeatedly, and wherein no matter how many times the steps b) through d) are performed, the same relative positions of the cells and wires, determined in the step a) are maintained, and

wherein in the step a), the relative positions of the cells and wires are determined so that the area of the integrated circuit is minimized.

18. A method of physical design for an integrated circuit made up of multiple cells, each cell includes a plurality of elements and performs a logic function, the method comprising the steps of:

a) determining relative positions of the cells and wires interconnecting the cells together in the integrated circuit;

b) evaluating a performance of the integrated circuit;

c) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step b); and

d) changing the performance of the candidate cell selected in the step c),

wherein the steps b), c) and d) are performed repeatedly, and wherein no matter how many times the steps b) through d) are performed, the same relative positions of the cells and wires, determined in the step a), are maintained, and

wherein in the step a), the relative positions of the cells and wires are determined so that the cells are placed at a uniform density in the integrated circuit.

19. A method of physical design for an integrated circuit made up of multiple cells, each cell includes a plurality of elements and performs a logic function, the method comprising the steps of:

a) determining relative positions of the cells and wires interconnecting the cells together in the integrated circuit;

b) evaluating a performance of the integrated circuit;

c) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step b); and

d) changing the performance of the candidate cell selected in the step c),

wherein the steps b), c) and d) are performed repeatedly, and wherein no matter how many times the steps b) through d) are performed, the same relative positions of the cells and wires, determined in the step a), are maintained, and

wherein in the step a), the cells are arranged in columns and rows, and wherein in the step b), the area of the integrated circuit is estimated from a product of a maximum cell row length and a maxim cell column length.

20. A method of physical design for an integrated circuit made up of multiple cells, each cell includes a plurality of elements and performs a logic function, the method comprising the steps of:

a) determining relative positions of the cells and wires interconnecting the cells together in the integrated circuit;

b) evaluating a performance of the integrated circuit;

c) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a); and

d) changing the performance of the candidate cell selected in the step c),

wherein the steps b), c) and d) are performed repeatedly, and wherein no matter how many times the steps b) through d) are performed, the same relative positions of the cells and wires, determined in the step a), are maintained, and

wherein in the step b), it is estimated how the shape of at least one of the wires changes when the area of the cell, having had its characteristic changed in the step d), changes, and the performance of the integrated circuit is evaluated while taking the estimated wire shape change into account.

21. A method of physical design for an integrated circuit made up of multiple cells, the method comprising the steps of:

a) evaluating the overall performance of the integrated circuit;

b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a); and

c) changing the performance of the candidate cell selected in the step b),

wherein the steps a), b) and c) are performed repeatedly, and

wherein in the step a), the size of transistors, which make up each said cell, is optimized with the area and performance of the cell taken into account, and then the performance of the cell, made up of the transistors of the optimized size, is evaluated.

22. The method of claim 21, further comprising the step of:

a′

) determining relative positions of the cells and wires interconnecting the cells together in the integrated circuit,

wherein no matter how many times the steps a) through c) are performed, the same relative positions of the cells and wires, determined in the step a′

), are maintained.

23. The method of claim 21, wherein each said cell should have a minimum area initially, and wherein in the step c), the performance of the candidate cell is changed by allowing the candidate cell to just increase its area.