Method and system for power node current waveform modeling
First Claim
1. A method for modeling characteristics of a logical circuit block, comprising:
- receiving input of a first plurality of values corresponding to times at which an output voltage of said logical circuit block reaches selected predetermined fractions of a supply voltage; and
generating a second time value for which said output voltage reaches a different predetermined fraction of said supply voltage by multiplying each of said plurality of values by a corresponding one of a set of coefficients that statistically relate said first plurality of input values to said second time value, and summing the multiplied values to produce a resulting time at which said output voltage reaches said different predetermined fraction of said supply voltage.
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Abstract
A method and system for power node current waveform modeling provides improved accuracy for logic gate and functional block power node current models in computer-based verification and design tools. An output voltage waveform is generated, with each point a linear function of a set of input values corresponding to times at which the output voltage reaches predetermined fractions of the supply voltage. A set of coefficients is used for each point, as each output voltage has a different linear dependency on the input values. The output voltage waveform model is differentiated and multiplied by an effective load capacitance to determine an output current waveform. The method and system retain compatibility with existing software by using input values already present in the digital simulation models (e.g., delay times) that yield a subset of output voltage points. The coefficients of the model are predetermined for a circuit from principle components analysis.
31 Citations
24 Claims
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1. A method for modeling characteristics of a logical circuit block, comprising:
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receiving input of a first plurality of values corresponding to times at which an output voltage of said logical circuit block reaches selected predetermined fractions of a supply voltage; and
generating a second time value for which said output voltage reaches a different predetermined fraction of said supply voltage by multiplying each of said plurality of values by a corresponding one of a set of coefficients that statistically relate said first plurality of input values to said second time value, and summing the multiplied values to produce a resulting time at which said output voltage reaches said different predetermined fraction of said supply voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
differentiating said output voltage waveform representation; and
multiplying a result of said differentiating by an effective load capacitance to produce current values representing an output current waveform.
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4. The method of claim 3, wherein said receiving, generating, differentiating, and multiplying are repeated for multiple logical circuit blocks resulting in a plurality of output current waveforms and further comprising summing said output current waveforms to provide a pin current for an integrated circuit package containing said logical circuit blocks.
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5. The method of claim 2, wherein said first plurality of input values comprises a third time value corresponding to a supply voltage fraction of 0.3, a fourth time value corresponding to a supply voltage fraction of 0.5 and a fifth time value corresponding to a supply voltage fraction of 0.7, and wherein said coefficient corresponding to said third time value and said coefficient corresponding to said fifth time value are equal in magnitude and opposite in sign, whereby said generating may be performed in conformity with a delay time and a rise time of said logical circuit block.
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6. The method of claim 2, wherein said first plurality of input values comprises a third time value corresponding to a supply voltage fraction of 0.5, a fourth time value corresponding to another supply voltage fraction less than 0.5 by a predetermined amount, and a fifth time value corresponding to a supply voltage fraction greater than 0.5 by said predetermined amount, and wherein said coefficient corresponding to said fourth time value and said fifth time value are equal in magnitude and opposite in sign, whereby said generating may be performed in conformity with a delay time and a rise time of said logical circuit block.
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7. The method of claim 1, wherein said first plurality of input values comprises a third time value corresponding to a supply voltage fraction of 0.3, a fourth time value corresponding to a supply voltage fraction of 0.5 and a fifth time value corresponding to a supply voltage fraction of 0.7, and wherein said coefficient corresponding to said third time value and said coefficient corresponding to said fifth time value are equal in magnitude and opposite in sign, whereby said generating may be performed in conformity with a delay time and a rise time of said logical circuit block.
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8. The method of claim 1, further comprising:
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simulating said logical circuit block over a variety of input waveforms and circuit conditions to produce a plurality of output voltage waveforms for said logical circuit block; and
determining said set of coefficients each relating a time at which said output voltage waveform reaches said selected predetermined fractions of said supply voltage to times at which said output voltage waveform reaches different predetermined fractions of said supply voltage via a statistical reduction of said plurality of output voltage waveforms that maximizes the variance of times at which said output voltage waveforms reach said selected predetermined fractions of said supply voltage and minimizes the variance of other times at which said output voltage waveforms reach said different predetermined fractions of said output voltage.
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9. A computer program product for use with a workstation computer, wherein said computer program product comprises signal bearing media containing program instructions for execution within said workstation computer for modeling characteristics of a logical circuit block, wherein said program instructions comprise program instructions for:
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receiving input of a first plurality of input values corresponding to times at which an output voltage of said logical circuit block reaches selected predetermined fractions of a supply voltage; and
generating a second time value for which said output voltage reaches a different predetermined fraction of said supply voltage by multiplying each of said first plurality of input values by a corresponding one of a set of coefficients that statistically relate said first plurality of input values to said second time value, and summing the multiplied values to produce a resulting time at which said output voltage reaches said different predetermined fraction of said supply voltage. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
differentiating said output voltage waveform representation; and
multiplying a result of said differentiating by an effective load capacitance to produce current values representing an output current waveform.
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12. The computer program product of claim 11, wherein said program instructions further comprise program instructions for repeating said receiving, generating, differentiating, and multiplying for multiple logical circuit blocks resulting in a plurality of output current waveforms and further comprising program instructions for summing said output current waveforms to provide a pin current for an integrated circuit package containing said logical circuit blocks.
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13. The computer program product of claim 10, wherein said plurality of input values comprises a third time value corresponding to a supply voltage fraction of 0.3, a fourth time value corresponding to a supply voltage fraction of 0.5 and a fifth time value corresponding to a supply voltage fraction of 0.7, and wherein said coefficient corresponding to said third time value and said coefficient corresponding to said fifth time value are equal in magnitude and opposite in sign, whereby said generating may be performed in conformity with a delay time and a rise time of said logical circuit block.
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14. The computer program product of claim 10, wherein said plurality of input values comprises a third time value corresponding to a supply voltage fraction of 0.5, a fourth time value corresponding to another supply voltage fraction less than 0.5 by a predetermined amount, and a fifth time value corresponding to a supply voltage fraction greater than 0.5 by said predetermined amount, and wherein said coefficient corresponding to said fourth time value and said fifth time value are equal in magnitude and opposite in sign, whereby said generating may be performed in conformity with a delay time and a rise time of said logical circuit block.
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15. The computer program product of claim 9, wherein said plurality of input values comprises a third time value corresponding to a supply voltage fraction of 0.3, a fourth time value corresponding to a supply voltage fraction of 0.5 and a fifth time value corresponding to a supply voltage fraction of 0.7, and wherein said coefficient corresponding to said third time value and said coefficient corresponding to said fifth time value are equal in magnitude and opposite in sign, whereby said generating may be performed in conformity with a delay time and a rise time of said logical circuit block.
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16. The computer program product of claim 9, wherein said program instructions further comprise program instructions for:
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simulating said logical circuit block over a variety of input waveforms and circuit conditions to produce a plurality of output voltage waveforms for said logical circuit block; and
determining said set of coefficients each relating a time at which said output voltage waveform reaches said selected predetermined fractions of said supply voltage to times at which said output voltage waveform reaches different predetermined fractions of said supply voltage via a statistical reduction of said plurality of output voltage waveforms that maximizes the variance of times at which said output voltage waveforms reach said selected predetermined fractions of said supply voltage and minimizes the variance of other times at which said output voltage waveforms reach said different predetermined fractions of said output voltage.
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17. A workstation comprising:
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a memory for storing program instructions and data values for modeling characteristics of a logical circuit block;
a processor for executing said program instructions, wherein said program instructions comprise program instructions for receiving input of a first plurality of input values corresponding to times at which an output voltage of said logical circuit block reaches selected predetermined fractions of a supply voltage, and generating a second time value for which said output voltage reaches a different predetermined fraction of said supply voltage by multiplying each of said first plurality of input values by a corresponding one of a set of coefficients that statistically relate said first plurality of input values to said second time value, and summing the multiplied values to produce a resulting time at which said output voltage reaches said different predetermined fraction of said supply voltage. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
differentiating said output voltage waveform representation; and
multiplying a result of said differentiating by an effective load capacitance to produce current values representing an output current waveform.
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20. The workstation of claim 19, wherein said program instructions for receiving, generating, differentiating, and multiplying are repeated for multiple logical circuit blocks resulting in a plurality of output current waveforms and further comprising program instructions for summing said output current waveforms to provide a pin current for an integrated circuit package containing said logical circuit blocks.
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21. The workstation of claim 18, wherein said plurality of input values comprises a third time value corresponding to a supply voltage fraction of 0.3, a fourth time value corresponding to a supply voltage fraction of 0.5 and a fifth time value corresponding to a supply voltage fraction of 0.7, and wherein said coefficient corresponding to said third time value and said coefficient corresponding to said fifth time value are equal in magnitude and opposite in sign, whereby said generating may be performed in conformity with a delay time and a rise time of said logical circuit block.
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22. The workstation of claim 18, wherein said plurality of input values comprises a third time value corresponding to a supply voltage fraction of 0.5, a fourth time value corresponding to another supply voltage fraction less than 0.5 by a predetermined amount, and a fifth time value corresponding to a supply voltage fraction greater than 0.5 by said predetermined amount, and wherein said coefficient corresponding to said fourth time value and said fifth time value are equal in magnitude and opposite in sign, whereby said generating may be performed in conformity with a delay time and a rise time of said logical circuit block.
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23. The workstation of claim 17, wherein said plurality of input values comprises a third time value corresponding to a supply voltage fraction of 0.3, a fourth time value corresponding to a supply voltage fraction of 0.5 and a fifth time value corresponding to a supply voltage fraction of 0.7, and wherein said coefficient corresponding to said third time value and said coefficient corresponding to said fifth time value are equal in magnitude and opposite in sign, whereby said generating may be performed in conformity with a delay time and a rise time of said logical circuit block.
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24. The workstation of claim 17, wherein said program instructions further comprise program instructions for:
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simulating said logical circuit block over a variety of input waveforms and circuit conditions to produce a plurality of output voltage waveforms for said logical circuit block; and
determining said-set of coefficients each relating a time at which said output voltage waveform reaches said selected predetermined fractions of said supply voltage to times at which said output voltage waveform reaches different predetermined fractions of said supply voltage via a statistical reduction of said plurality of output voltage waveforms that maximizes the variance of times at which said output voltage waveforms reach said selected predetermined fractions of said supply voltage and minimizes the variance of other times at which said output voltage waveforms reach said different predetermined fractions of said output voltage.
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Specification