Ultra small size vertical MOSFET device and method for the manufacture thereof

• US 6,770,534 B2
• Filed: 07/11/2003
• Issued: 08/03/2004
• Est. Priority Date: 03/28/2001
• Status: Expired due to Term

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Lee, Seong Jae, Cho, Wonju, Park, Kyoung Wan
• Primary Examiner(s): Pham, Long
• Application Number:
  US10/617,183
• Publication Number:
  US 20040007737A1
• Time in Patent Office: 389 Days
• Field of Search: 438/156, 438/173, 438/192, 438/206, 438/212, 438/268
• US Class Current: 438/268
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: Y10S 977/712 formed from plural layers of nanosized material, e.g. stacked structures
• CPC Class Codes: Y10S 977/721 On a silicon substrate
• CPC Class Codes: Y10S 977/723 On an electrically insulating substrate
• CPC Class Codes: Y10S 977/887 Nanoimprint lithography, i.e. nanostamp

Abstract

The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface. Then, an annealing process is carried out to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source contact, a drain contact and a vertical channel. Finally, a gate electrode is formed on side walls of the vertical channel.

Claims

1. A method for manufacturing an ultra small size vertical MOSFET device, the method comprising the steps of:

a) preparing an SOI substrate including a single crystal substrate, an oxide layer formed upon the single crystal substrate and a first single crystal silicon layer formed upon the oxide layer;

b) forming a first silicon conductive layer by doping an impurity of a high concentration into the first single crystal silicon layer;

c) forming a second single crystal silicon layer and a second silicon conductive layer on the first silicon conductive layer, wherein the second single crystal silicon layer has the impurity of a low concentration and the second silicon conductive layer has the impurity of a high concentration;

d) patterning the second silicon conductive layer and the second single crystal silicon layer vertically into a first predetermined configuration;

e) forming a gate insulating layer on the first silicon conductive layer, the second single crystal silicon layer and the second silicon conductive layer;

f) carrying out an-annealing process to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source contact, a drain contact and a vertical channel; and

g) forming a gate electrode on side walls of the vertical channel, wherein the gate electrode encompasses the channel.

2. The method as recited in claim 1, wherein the step b) is carried out by using a method selected from the group consisting of an ion implantation and a vapor diffusion technique.

3. The method as recited in claim 1, wherein the step c) is carried out by using a method selected from the group consisting of a CVD technique and a MBE technique.

4. The method as recited in claim 1, wherein the second silicon conductive layer is formed using a material selected from the group consisting of an amorphous silicon and a poly-crystal silicon by the CVD technique.

5. The method as recited in claim 1, wherein the step d) is carried out using an etch mask by a dry etch process.

6. The method as recited in claim 5, wherein the etch mask includes a material selected from the group consisting of a photoresist, an oxide and a nitride layer.

7. The method as recited in claim 1, wherein the step f) is carried out in a temperature ranging from approximately 700°

C. to approximately 1,000°

C. in a furnace selected from the group consisting of an electrical furnace and a rapid thermal annealing (RTA) furnace.

8. The method as recited in claim 1, wherein the gate insulating layer includes a material selected from the group consisting of a thermal oxide layer, a nitride layer, a CVD oxide layer and a CVD nitride layer.

9. The method as recited in claim 1, wherein the step g) includes the steps of:

g1) forming a third silicon conductive layer on the gate insulating layer;

g2) forming a first ILD layer on the third silicon conductive layer; and

g3) patterning the third silicon conductive layer and the first ILD layer into a second predetermined configuration, thereby obtaining the gate electrode.

10. The method as recited in claim 9, wherein the third conductive layer is formed by the CVD technique using a material selected from the group consisting of an amorphous silicon or a poly-crystal silicon.

11. The method as recited in claim 1, after the step g), further comprising the steps of:

h) forming a second ILD layer on the gate electrode

i) patterning the second ILD layer into a third predetermined configuration, thereby obtaining contact holes; and

j) depositing a metal or a silicon conductive layer in the holes, thereby forming a source, a drain and a gate electrode interconnections.