Low temperature plasma Si or SiGe for MEMS applications

• US 6,770,569 B2
• Filed: 08/01/2002
• Issued: 08/03/2004
• Est. Priority Date: 08/01/2002
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Foerstner, Juergen A., Smith, Steven M., Roop, Raymond Mervin
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Geyer, Scott B.
• Application Number:
  US10/210,315
• Publication Number:
  US 20040023429A1
• Time in Patent Office: 733 Days
• Field of Search: 438/106, 438/117, 438/758, 438/767
• US Class Current: 438/758
• CPC Class Codes: B81B 2201/018 Switches not provided for in B81B2201/014 - B81B2201/016
• CPC Class Codes: B81B 2201/0292 Sensors not provided for in B81B2201/0207 - B81B2201/0285
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/0038 Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• CPC Class Codes: B81C 2201/0164 by doping the layer
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: H01G 5/18 due to change in inclination, e.g. by flexing, by spiral wrapping

Abstract

A method is provided for making a MEMS structure (69). In accordance with the method, a CMOS substrate (51) is provided which has interconnect metal (53) deposited thereon. A MEMS structure is created on the substrate through the plasma assisted chemical vapor deposition (PACVD) of a material selected from the group consisting of silicon and silicon-germanium alloys. The low deposition temperatures attendant to the use of PACVD allow these materials to be used for MEMS fabrication at the back end of an integrated CMOS process.

Claims

1. A method for making a MEMS structure, comprising the steps of:

providing a CMOS substrate having interconnect metal deposited thereon; and

creating a MEMS structure on the substrate through the plasma assisted chemical vapor deposition of a material selected from the group consisting of silicon and silicon-germanium alloys.

2. The method of claim 1, wherein the MEMS structure is a sensor.

3. The method of claim 1, wherein the MEMS structure is an actuator.

4. The method of claim 1, wherein the interconnect metal comprises gold.

5. The method of claim 1, wherein the material is doped as it is deposited.

6. The method of claim 1, wherein the materiel is deposited at a temperature of less than about 450°

C.

7. The method of claim 1, wherein the material is deposited at a temperature of less than about 350°

C.

8. The method of claim 1, wherein the material is deposited at a temperature of less than about 300°

C.

9. The method of claim 1, wherein the material is deposited at a temperature of less than about 250°

C.

10. The method of claim 1, wherein the material comprises amorphous hydrogenated silicon.

11. The method of claim 1, wherein said CMOS substrate has at least a first surface region thereon comprising a first material selected from the group consisting of silicon, silicon oxide and gallium arsenide, and at least a second surface region thereon comprising a second material selected from the group consisting of silicon oxide and polyimide.

12. The method of claim 11, further comprising the steps of:

forming a layer of a third material which extends over at least a portion of the first and second regions, wherein the third material is selected from the group consisting of silicon and silicon-germanium alloys, and wherein the layer of the third material is formed at a temperature of less than about 450°

C. through a plasma assisted chemical vapor deposition process; and

removing at least a portion of the second material from underneath the layer of the third material so as to form a micromechanical deflection element comprising the third material.

13. The method of claim 12, wherein the layer of the third material is formed at a temperature of less than about 400°

C.

14. The method of claim 12, wherein the layer of the third material is formed at a temperature of less than about 350°

C.

15. The method of claim 12, wherein the layer of the third material is formed at a temperature of less than about 300°

C.

16. The method of claim 12, wherein the layer of the third material is formed at a temperature of less than about 250°

C.

17. The method of claim 12, wherein the third material comprises silicon.

18. The method of claim 12, wherein the third material comprises germanium.

19. The method of claim 12, wherein the third layer is doped as it is formed.

20. The method of claim 19, wherein the dopant used to dope the third layer is boron or phosphorous.

21. The method of claim 12, wherein the micromechanical deflection element is a component of a sensor.

22. The method of claim 12, wherein the micromechanical deflection element is a component of an actuator.

23. The method of claim 12, wherein the third material comprises amorphous hydrogenated silicon.

24. The method of claim 1, wherein the CMOS substrate has circuitry defined thereon for supporting an RF MEMS switch, and wherein the step of creating a MEMS structure on the substrate comprises the steps of:

applying a sacrificial layer to at least a portion of the substrate;

forming a structural element of an RF MEMS switch that extends over at least a portion of the sacrificial layer;

forming, through the use of a plasma assisted chemical vapor deposition process, an electrode on a surface of the structural element, the electrode comprising a material selected from the group consisting of silicon and silicon-germanium alloys; and

removing at least a portion of the sacrificial layer from underneath the structural element so as to release the structural element.

25. The method of claim 24, wherein the structural element is formed by depositing and patterning a layer of SiON over the sacrificial layer.

26. The method of claim 24, wherein the sacrificial layer comprises a polyimide.

27. The method of claim 24, wherein the circuitry comprises gold.

28. The method of claim 24, wherein the structural element is formed at a temperature of less than about 350°

C.

29. The method of claim 24, wherein the structural element is formed at a temperature of less than about 250°

C.

30. The method of claim 24, wherein the material comprises amorphous hydrogenated silicon.